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n uc505 june 3 0 , 2016 page 1 of 130 rev 1.0 6 nuc505 series datasheet arm ? cortex ? - m 4 32 - bit microcontroller numicro ? family nuc 505 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvot on.com
n uc505 june 3 0 , 2016 page 2 of 130 rev 1.0 6 nuc505 series datasheet table of contents 1 general description ................................ .............................. 8 2 features ................................ ................................ ................ 9 nuc505 features ................................ ................................ .......... 9 2.1 3 abbreviations ................................ ................................ ....... 14 abbreviations ................................ ................................ ............... 14 3.1 4 parts information li st and pin configura tion ..................... 15 selection guide ................................ ................................ ............ 15 4.1 4.1.1 numicro ? nuc505 base series selection guide ................................ ...... 15 4.1.2 numicro ? nuc505 base series naming rule ................................ .......... 16 pin configuration ................................ ................................ .......... 17 4.2 4.2.1 numicro ? nuc505dla lqfp 48 - pin ................................ .................... 17 4.2.2 numicro ? NUC505DL13Y lqfp 48 - pin ................................ ................. 18 4.2.3 numicro ? nuc505yla qfn 48 - pin ................................ ...................... 19 4.2.4 numicro ? nuc505yla2y qfn 48 - pin ................................ .................. 20 4.2.5 numicro ? nuc505dsa lqfp 64 - pin ................................ .................... 21 4.2.6 numicro ? nuc505ds13y lqfp 64 - pn ................................ .................. 22 4.2.7 numicro ? nuc505yo13y qfn 88 - pin ................................ .................. 23 pin description ................................ ................................ ............. 24 4.3 4.3.1 numicro ? nuc505dla lqfp 48 - pin description ................................ ...... 24 4.3.2 numicro ? NUC505DL13Y lqfp 48 - pin description ................................ ... 28 4.3.3 numicro ? nuc505yla qfn 48 - pin description ................................ ....... 33 4.3.4 numicro ? nuc505yla2y qfn 48 - pin description ................................ .... 37 4.3.5 numicro ? nuc505dsa lqfp 64 - pin description ................................ ..... 42 4.3.6 numicro ? nuc505ds13y lqfp 64 - pin description ................................ .. 48 4.3.7 numicro ? nuc505yo13y qfn 88 - pin description ................................ ... 54 4.3.8 summary gpio multi - function pin description ................................ ......... 62 4.3.9 gpio multi - function pin summary ................................ ........................ 64 5 block diagram ................................ ................................ ...... 68 numicro ? nuc505 series block diagram ................................ ............. 68 5.1 6 functional descripti on ................................ ........................ 69 arm ? cortex ? - m4 core ................................ ................................ .. 69 6.1 system manager ................................ ................................ .......... 72 6.2
n uc505 june 3 0 , 2016 page 3 of 130 rev 1.0 6 nuc505 series datasheet 6.2.1 overview ................................ ................................ ...................... 72 6.2.2 system reset ................................ ................................ ................ 72 6.2.3 system power - on setting ................................ ................................ .. 73 6.2.4 system power distribution ................................ ................................ . 73 6.2.5 system memory mapping ................................ ................................ .. 74 6.2.6 sram memory organization ................................ .............................. 76 6.2.7 ahb bus arbitration ................................ ................................ ......... 78 6.2.8 system timer (systick) ................................ ................................ ..... 80 6.2.9 nested vectored interrupt control (nvic) ................................ ............... 81 clock controller ................................ ................................ ............ 84 6.3 6.3.1 overview ................................ ................................ ...................... 84 6.3.2 clock diagram ................................ ................................ ............... 85 6.3.3 clock generator ................................ ................................ ............. 86 6.3.4 power - down mode clock ................................ ................................ .. 87 general purpose i/o (gpio) ................................ ............................ 88 6.4 6.4.1 overview ................................ ................................ ...................... 88 6.4.2 features ................................ ................................ ...................... 88 timer controller (timer) ................................ ................................ 90 6.5 6.5.1 overview ................................ ................................ ...................... 90 6.5.2 features ................................ ................................ ...................... 9 0 pwm generator and capture timer (pwm) ................................ .......... 91 6.6 6.6.1 overview ................................ ................................ ...................... 91 6.6.2 features ................................ ................................ ...................... 91 watchdog timer (wdt) ................................ ................................ .. 92 6.7 6.7.1 overview ................................ ................................ ...................... 92 6.7.2 features ................................ ................................ ...................... 92 window wat chdog timer (wwdt) ................................ ..................... 92 6.8 6.8.1 overview ................................ ................................ ...................... 92 6.8.2 features ................................ ................................ ...................... 92 real time clock (rtc) ................................ ................................ ... 93 6.9 6.9.1 overview ................................ ................................ ...................... 93 6.9.2 features ................................ ................................ ...................... 93 uart interface controller (uart) ................................ ..................... 94 6.10 6.10.1 overview ................................ ................................ ...................... 94
n uc505 june 3 0 , 2016 page 4 of 130 rev 1.0 6 nuc505 series datasheet 6.10.2 featu res ................................ ................................ ...................... 94 i 2 c serial interface controller (master/slave) ................................ ........ 95 6.11 6.11.1 overview ................................ ................................ ...................... 95 6.11.2 features ................................ ................................ ...................... 96 serial peripheral interface (spi) ................................ ........................ 97 6.12 6.12.1 overview ................................ ................................ ...................... 97 6.12.2 featu res ................................ ................................ ...................... 97 spi memory interface controller (spim) ................................ .............. 98 6.13 6.13.1 overview ................................ ................................ ...................... 98 6.13.2 features ................................ ................................ ...................... 98 i 2 s controller with internal audio codec (i 2 s) ................................ ...... 99 6.14 6.14.1 overview ................................ ................................ ...................... 99 6.14.2 featu res ................................ ................................ ...................... 99 usb 2.0 device controller (usbd) ................................ ................... 100 6.15 6.15.1 overview ................................ ................................ .................... 100 6.15.2 features ................................ ................................ .................... 100 usb 1.1 host controller (usbh) ................................ ..................... 101 6.16 6.16.1 overview ................................ ................................ .................... 101 6.16.2 featu res ................................ ................................ .................... 101 secure - digital host controller (sdhc) ................................ .............. 102 6.17 6.17.1 overview ................................ ................................ .................... 102 6.17.2 features ................................ ................................ .................... 102 12 - bit analog - to - digital converter (adc) ................................ ............ 103 6.18 6.18.1 overview ................................ ................................ .................... 103 6.18.2 featu res ................................ ................................ .................... 103 7 electrical character istics ................................ ................ 104 absolute maximum ratings ................................ ............................ 104 7.1 dc characteristics ................................ ................................ ...... 105 7.2 ac electrical characteristics ................................ .......................... 108 7.3 7.3.1 external 12 mhz crystal ................................ ................................ . 108 7.3.2 external 12 mhz high speed oscillator ................................ ............... 108 7.3.3 typical crystal application circuits ................................ ..................... 108 7.3.4 internal 32 khz low speed oscillator ................................ .................. 109 analog characteristics ................................ ................................ .. 110 7.4
n uc505 june 3 0 , 2016 page 5 of 130 rev 1.0 6 nuc505 series datasheet 7.4.1 specifications of 12 - bit saradc ................................ ....................... 110 7.4.2 specifications of 24 - bit delta - sigma codec ................................ ......... 112 7.4.3 specification of ldo ................................ ................................ ...... 113 7.4.4 specification of low voltage reset ................................ .................... 114 7.4.5 specifications of power - on reset ................................ ...................... 114 7.4.6 usb phy specifications ................................ ................................ . 116 7.4.7 i 2 c dynamic characteristics ................................ ............................. 118 7.4.8 spi dynamic characteristics ................................ ............................ 119 7.4.9 i 2 s dynamic characteristics ................................ ............................. 121 8 application circuit ................................ .............................. 123 9 package dimensions ................................ ............................ 124 lq fp 48l (7x7x1.4mm footprint 2.0mm) ................................ ............ 124 9.1 qfn 48 (7x7x0.8mm) ................................ ................................ ... 125 9.2 lqfp 64l (7x7x1.4mm footprint 2.0mm) ................................ ............ 126 9.3 qfn 88 (10x10x0.9mm) ................................ ................................ 127 9.4 10 revision history ................................ ................................ .. 129
n uc505 june 3 0 , 2016 page 6 of 130 rev 1.0 6 nuc505 series datasheet list of figures figure 4.1 - 1 numicro ? nuc505 base series selection code ................................ ....................... 16 figure 4.2 - 1 numicro ? nuc505dla lqfp 48 - pin diagram ................................ .......................... 17 figure 4.2 - 2 numicro ? NUC505DL13Y lqfp 48 - pin diagram ................................ ...................... 18 figure 4.2 - 3 numicro ? nuc505yla qfn 48 - pin diagr am ................................ ............................ 19 figure 4.2 - 4 numicro ? nuc505yla2y qfn 48 - pin diagram ................................ ....................... 20 figure 4.2 - 5 numicro ? nuc505dsa lqfp 64 - pin diagram ................................ ......................... 21 figure 4.2 - 6 numicro ? nuc505ds13y lqfp 64 - pin diagram ................................ ..................... 22 figure 4.2 - 7 numicro ? nuc505yo13y qfn 88 - pin diagram ................................ ....................... 23 figure 5.1 - 1 numicro ? nuc505 block diagram ................................ ................................ ............ 68 figure 6.1 - 1 cortex ? - m4 block diagram ................................ ................................ ........................ 69 figure 6.2 - 1 numicro ? nuc505 power distribution diagram ................................ ........................ 74 figure 6.2 - 2 sram block diagram ................................ ................................ ................................ 76 figure 6.2 - 3 sram memory organization ................................ ................................ ..................... 77 figure 6.2 - 4 vector map module block ................................ ................................ .......................... 78 figure 6.3 - 1 clock generator global view diagram ................................ ................................ ...... 85 figure 6.3 - 2 clock generator block diagram ................................ ................................ ................ 86 figure 6.3 - 3 crystal oscillator circuit ................................ ................................ ............................ 87 figure 6.4 - 1 i/o pin block diagram ................................ ................................ ............................... 88 figure 6.11 - 1 i 2 c bus timing ................................ ................................ ................................ ......... 95 figure 7.3 - 1 typical crystal application circuit ................................ ................................ ........... 109 figure 7.4 - 1 power - up ramp condition ................................ ................................ ...................... 115 figure 7.4 - 2 i 2 c timing diagram ................................ ................................ ................................ . 118 figure 7.4 - 3 spi master mode timing diagram ................................ ................................ .......... 119 figure 7.4 - 4 spi slave mode timing diagram ................................ ................................ ............ 120 figure 7.4 - 5 i2s master mode timing diagram ................................ ................................ ........... 122 figure 7.4 - 6 i 2 s slave mode timing diagram ................................ ................................ .............. 122
n uc505 june 3 0 , 2016 page 7 of 130 rev 1.0 6 nuc505 series datasheet list of tables table 3.1 - 1 list of abbreviations ................................ ................................ ................................ .... 14 table 4.1 - 1 numicro ? nuc505 base series selection guide ................................ ....................... 15 table 4.3 - 1 nuc505 gpio multi - function table ................................ ................................ ............ 67 table 6.2 - 1 system power - on setting guide ................................ ................................ ................. 73 table 6.2 - 2 address space assignments for on - chip controllers ................................ ................ 75 table 6.2 - 3 ahb bus priority order in fixed priority mode ................................ ........................... 79 table 6.2 - 4 exception model ................................ ................................ ................................ ....... 82 table 6.2 - 5 interrupt number table ................................ ................................ ............................... 83 table 6.3 - 1 recommended load capacitance values and resistance values. .......................... 87
n uc505 june 3 0 , 2016 page 8 of 130 rev 1.0 6 nuc505 series datasheet 1 general description the numicro ? nuc505 s eries 32 - bit microcontrollers are embedded with arm ? cortex ? - m 4f core for consumer and industrial applications which need high computing power and rich communication interfaces. the arm ? cortex ? - m4f core within numicro ? nuc505 series can run up to 100 mhz and support dsp extensions and floating point unit (fpu) function. the numicro ? nuc505 series supports 128 kbytes embedded sram with zero - wait state and 512 kb/ 2 mbytes embedded spi flash memory , and is equip ped with plenty of high performance peripheral devices, such as 24 - bit audio codec, usb2.0 high - speed device, usb2.0 full - speed host, and other peripheral. the numicro ? nuc505 series is suitable for a wide range of applications such as: ? audio and wireless audio applications ? thermal p rinter did not find any incorrect format ? gps tracker / vtdr ( vehicle travelling data recorder ) ? others high performance or data i n tensive computing applications key features: ? core arm ? cortex ? - m4f core running up to 100 mhz (with dsp and fpu) ? memory 128 kb of sram with zero - wait state 512 kb/ 2 mb of spi flash ? security for code protect ion 128 - bit key for code protection against pirating up to 15 times programming the key ? clock control 12 mhz crystal oscillator input up to two plls for system clock and audio ? up to 12 co mmunication interfaces usb 2.0 hs device interface up to two usb 2.0 fs host interfaces up to three uarts up to three spis up to two i 2 c interfaces ( u p to 1 mhz) sd host ? gpio supports up to 25 /35/ 52 gpios for qfn88/lqfp64/lqfp48 respectively ? timer supports four sets of 32 - bit timers supports two watchdog timers (independent and window) ? rtc supports external power pin v bat 32 b ytes spare registers internal 32.768 khz rc with calibration ? i 2 s supports master or slave mode operation supports pcm mode a, pcm mode b, i 2 s and msb justified data format supports dma mode ? audio codec embedded stereo 24 - bit sigma - delta codec mic/line - in - thdn: - 80 db, dynamic range snr: 90 db (a - weighted) headphone output - thdn: - 60db, dynamic range snr: 93 db (a - weighted) sample rate: 8 khz to 96 khz ? 12 - bit adc analog input voltage range: 0~ av dd supports single 12 - bit sar adc conversion up to 8 channels u p to 1 msps conversion with adc_ch1, and up to 200 ksps with other channel s (except adc_ch0). ? built - in ldo with operating voltage 3.3v ? low voltage detector (lvd) with 2 levels: 2.8v / 2.6v ? low voltage reset (lvr) threshold voltage level: 2.4 v ? packages lqfp48, lqfp64, qfn88 temperature range: - 40 ~+85
n uc505 june 3 0 , 2016 page 9 of 130 rev 1.0 6 nuc505 series datasheet 2 features nuc 505 features 2.1 ? core arm ? cortex ? - m 4 f core run ning up to 100 mhz supports dsp extension with hardware divider supports ieee 754 compliant floating p oint unit (fpu) supports memory protection unit (mpu) one 24 - bit system timer supports power - down mode by wfi and wfe instructions single - cycle 32 - bit hardware multiplier supports programmable 16 level priorities of nested vectored interrupt controller ( nvi c) supports programmab le ma sk - able interrupts boots from s pi flash memory or usb device ? sram memory 128 kb embedded sram with zero - wait state supports by te - , half - word - and word - access ? spi m emory interface controller supports e xternal spi flash m emory supports code protection supports dma mode for code transfer from s pi flash m emory to sram supports cpu direct read f rom s pi flash m emory. supports s tandard (1 - bit), d ual (2 - bit), and q uad (4 - bit) i/o t ransfer m ode supports general spi master interface protocol ? embedded s pi flash 512 kb/ 2 mb spi flash configurable p rogram code / data allocation supports 2 - wire d icp update through swd/ice interface supports isp update supports s tandard (1 - bit) , d ual (2 - bit) , and q ua d (4 - bit) i/o t ransfer m ode supports 100 mhz clock for s tandard i/o t ransfer m ode supports 80 mhz clock for d ual and q uad i/o t ransfer m ode ? security for code protect ion 128 - bit key for code protection against pirating up to 15 times programming of the key ? clock control built - in 32.768 khz internal low speed rc oscillator (lirc) for rtc function,
n uc505 june 3 0 , 2016 page 10 of 130 rev 1.0 6 nuc505 series datasheet watchdog t imer and w ake - up operation supports 32.768 khz external low speed crystal oscillator (lxt) for rtc function and low - power system operation supports 12 mhz external high speed crystal oscillator (hxt) for precise timing operation supports one pll up to 240 mhz for high performance system operation . the external high speed crystal oscillator (hxt) is used as the clock source for the pll. ? i 2 s supports master or slave mode operation internal pll for frequency adjustment capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes supports mono and stereo audio data supports pcm mode a, pcm mode b, i 2 s and msb justified data format each provides t wo 16 - word fif o data buffers , one for transmit ting and the other for receiv ing generates interrupt requests when buffer levels cross a programmable boundary s upport s dma mode interface with internal or external audio codec ? audio c odec embedded stereo 24 - bit sigma - delta codec output adc - thdn: - 80 db, dynamic range snr: 90 db (a - weighted) headphone output - thdn: - 60db, dynamic range snr: 93 db (a - weighted) sample rate: 8 khz to 96 khz ? usb 2.0 high - s peed device 12 programmable endpoint s for control, bulk i n /o ut , interrupt and isochronous transfers 2k - b yte buffer auto suspend function r emote wake - up capability ? usb 2.0 full - s peed h ost fully compliant with usb r evision 1.1 specification open host controller interface (ohci) r evision 1.0 compatible full - s peed (12mbps) and low - s peed (1.5mbps) device supported control, bulk, interrupt and isochronous transfers supported ? sd host interface supports sd (secure digital) card and sd_host interface compliant with sd memory card specification version 2.0
n uc505 june 3 0 , 2016 page 11 of 130 rev 1.0 6 nuc505 series datasheet supports 1 and 4 - bit modes supports 50 mhz to achieve 2 00 mbps at 3.3v operation supports dma master ? timer supports 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter independent clock source for each timer provides o ne - shot, p eriodic, t oggle and c ontinuous c ounting operation modes supports event counting function to count the event from external pin supports input capture function to capture or reset counter value ? watchdog timer supports m ultiple clock sources from lirc (default selection) , hxt and lxt 8 sel ectable time - out period from 1. 6ms ~ 26 .0sec (depend ing on clock source) interrupt or reset selectable on watchdog time - out ? window watchdog timer supports m ultiple clock sources from lirc (default selection) , hxt and lxt w indow set by 6 - bit counter with 11 - bit prescale interrupt or reset selectable on t ime - out ? gpio four i/o modes c mos /schmitt trigger input selectable i/o pin configured as interrupt source with edge trigger setting supports 5v - tolerance function (except pa .7~pa.0 and pd.4~pd.2 only support 3.3 v) supports u p to 52/35 (34) /25 (18) gpios for qfn88/ lqfp 64 / lqfp48 respectively ? uart supports up to three uarts C uart0, uart1 and uart2 supports 16 - byte fifos with programmable level trigger with uart0 supports 64 - byte fifos with programmable level trigger with uart1 and uart2 supports auto flow control ( n cts and n rts) with uart1 and uart2 supports irda (sir) function supports rs - 485 9 - bit mode and direction control uart1 and uart2 s upport lin function programmable baud - rate generator up to 1/16 system clock support s n cts and data wake - up function ? spi supports two set s of spi controller C spi0 and spi1 supports master or slave mode operation
n uc505 june 3 0 , 2016 page 12 of 130 rev 1.0 6 nuc505 series datasheet supports 1 - bit transfer mode configurable bit length of a transfer word from 8 to 32 - bit provides separate 8 - level depth transmit and receive fifo buffers supports msb first or lsb first transfer sequence supports the byte reorder function supports byte or word suspend mode supports 3 - wire d , no slave select signal, bi - direction interface supports up to 50 mhz ? i 2 c supports u p to two sets of i 2 c device s supports master/slave mode bidirectional data transfer between masters and slaves multi - master bus (no central master) arbitration between simultaneously transmitting masters without corruption of serial data on the bus serial clock synchronization allows devices with different bit rates to communicate via one serial bus serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer prog rammable clocks allow versatile rate control supports multiple address recognition (four slave address with mask option) supports smbus and pmbus supports speed up to 1mbps supports multi - address power - down wake - up function ? pwm four 16 - bit timers programmable duty control of output waveform (pwm) auto reload mode or one - shot pulse mode capture and compare function ? rtc supports external power pin rtc_vdd33 supports 32.768 k hz crystal oscillation circuit supports rtc counter (second, minute, hour) an d calendar counter (day, month, year) supports alarm registers (second, minute, hour, day, month, year) supports 32 bytes spare registers w ake up from deep power - d own mode or from power - d own mode supports w ake up from power - d own mode by input pin
n uc505 june 3 0 , 2016 page 13 of 130 rev 1.0 6 nuc505 series datasheet supports chip p ower - off by register setting supports p ower - on time - out for low battery protection ? a nalog to digital converter analog input voltage range: 0~ av dd supports single 12 - bit sar adc conversion 12 - bit resolution and 10 - bit accuracy is guaranteed u p to 1m sps conversion with adc_ch1 , and up to 200 ksps with others (except adc_ch0) . up to 8 external single - end ed analog input channels supports s ingle adc interrupt an a/d conversion can be triggered by s oftware control ? buil t - in ldo with operating voltage 3.3 v ? low voltage detector (lvd) with 2 levels: 2.8 v / 2.6v ? low voltage reset (lvr) threshold voltage level: 2.4 v ? power management advanced power management including deep power - d own, power - d own , idle and normal operating modes normal operating m ode ? cpu run s normally and all clocks on ; the current consumption is around 46 ma (at 96 mhz cpu clock) idle mode ? cpu clock stop, and all other clocks on power - d own m ode ? all clocks stop, except lxt and lirc, with sram retention ; the current consumption is around 7 0 0 u a deep power - d own m ode ? all clocks stop, except lxt and lirc, without sram retention ; the current consumption is around 7 ua ? operating temperature: - 4 0 ~ + 8 5 ? package s all green package (rohs) qfn 88 - pin (1 0 mm x 1 0 mm) lqfp 64 - pin (7mm x 7mm) lqfp 48 - pin (7mm x 7mm) qfn 48 - pin (7mm x 7mm)
n uc505 june 3 0 , 2016 page 14 of 130 rev 1.0 6 nuc505 series datasheet 3 abbreviations abbreviations 3.1 acronym description adc analog - to - digital converter apb advanced peripheral bus ahb a dvanced h igh - p erformance b us dma direct memory access fifo first in, first out fpu floating point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hxt 12 mhz e xternal high speed crystal oscillator icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 32.768 khz internal low speed rc oscillator lxt 32.768 k hz e xternal low speed crystal oscillator lvd low voltage detection mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pll phase - locked loop pwm pulse width modulation sd secure digital spi serial peripheral interface spim serial master interface controller sps samples per second tmr timer controller uart universal asynchronous receiver/transmitter usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3.1 - 1 list of abbreviations
n uc505 june 3 0 , 2016 page 15 of 130 rev 1.0 6 nuc505 series datasheet 4 parts information li st and pin configura tion selection guide 4.1 4.1.1 numicro ? nuc 505 base series selection guide [1]: * marked in the table means that only nuc505ds13y supports headphone out. [2]: the packages are not pin - to - pin compatible even though they are the same packages. lqfp64*: 7x7mm part number serial flash ( kb ) sram ( kb ) isp rom ( kb ) i / o timer (3 2 - b it ) connectivity i 2 s usb 2 . 0 hs device usb 2 . 0 fs host pwm (1 6 - b it ) 2 4 - b it a udio codec [1] digital mic adc ( 1 2 - b it ) rtc isp / icp package [2] i 2 c sd host spi uart nuc505dla 512 128 8 18 4 2 - 3 2 1 1 - - 1 5ch - lqfp48 NUC505DL13Y 2048 128 8 25 4 2 1 3 3 1 1 1 4 - 1 5ch lqfp48 nuc505yla 512 128 8 18 4 2 - 3 2 1 1 - - 1 5ch - qfn48 nuc505yla2y 512 128 8 25 4 2 1 3 3 1 1 1 4 - 1 5ch qfn48 nuc505dsa 512 128 8 34 4 2 1 3 3 1 1 1 4 1 5ch - lqfp64* nuc505ds13y 2048 128 8 35 4 2 1 3 3 1 1 1 4 * 1 8ch lqfp64* nuc505yo13y 2048 128 8 52 4 2 1 3 3 1 1 2 4 1 8ch qfn88 table 4.1 - 1 numicro ? nuc505 base series selection guide
n uc505 june 3 0 , 2016 page 16 of 130 rev 1.0 6 nuc505 series datasheet 4.1.2 numicro ? nuc 505 base series naming rule figure 4.1 - 1 numicro ? nuc505 base series selection code a: 512kbyte
n uc505 june 3 0 , 2016 page 17 of 130 rev 1.0 6 nuc505 series datasheet pin configuration 4.2 4.2.1 numicro ? nuc505 dla lqfp 48 - pin figure 4.2 - 1 numicro ? nuc505 dla lqfp 4 8 - pin diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 4 5 4 6 4 7 4 8 4 1 4 2 4 3 4 4 3 7 3 8 3 9 4 0 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 l q f p 4 8 - p i n n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 4 v d d x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t p a . 8 p a . 9 p a . 1 0 p a . 1 1 v d d p b . 0 p b . 1 p b . 2 u s b _ v b u s v s s a v d d a d c a v s s a d c p a . 0 p d . 4 p a . 2 p a . 3 p a . 4 v d d 1 2 v d d l d o _ c a p v s s p b . 1 5 p b . 3 p b . 4 p b . 5 a v d d h p l h p o u t r h p o u t a v s s h p v m i d a v d d c o d e c v d d 1 2 m i c 0 _ p m i c 0 _ n m i c _ b i a s p a . 1
n uc505 june 3 0 , 2016 page 18 of 130 rev 1.0 6 nuc505 series datasheet 4.2.2 numicro ? nuc505 dl13y lqfp 48 - pin figure 4.2 - 2 numicro ? nuc505 dl13y lqfp 48 - pin diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 4 5 4 6 4 7 4 8 4 1 4 2 4 3 4 4 3 7 3 8 3 9 4 0 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 l q f p 4 8 - p i n n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 3 v d d x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t v s s v b a t r t c _ r p w r r t c _ n r w a k e p a . 8 p a . 9 p a . 1 0 p a . 1 1 v d d p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 5 p b . 6 p b . 7 u s b _ v b u s p b . 8 p b . 9 v s s a v d d a d c a v s s a d c p a . 0 p a . 1 p a . 2 p a . 3 p a . 4 v d d 1 2 p b . 1 0 p b . 1 1 p b . 1 2 v d d v d d l d o _ c a p v s s
n uc505 june 3 0 , 2016 page 19 of 130 rev 1.0 6 nuc505 series datasheet 4.2.3 numicro ? nuc505 yla qfn 4 8 - pin figure 4.2 - 3 numicro ? nuc505 yla qfn 4 8 - pin diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 4 5 4 6 4 7 4 8 4 1 4 2 4 3 4 4 3 7 3 8 3 9 4 0 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 q f n 4 8 - p i n n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 4 v d d x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t p a . 8 p a . 9 p a . 1 0 p a . 1 1 v d d p b . 0 p b . 1 p b . 2 u s b _ v b u s v s s a v d d a d c a v s s a d c p a . 0 p d . 4 p a . 2 p a . 3 p a . 4 v d d 1 2 v d d l d o _ c a p v s s p b . 1 5 p b . 3 p b . 4 p b . 5 a v d d h p l h p o u t r h p o u t a v s s h p v m i d a v d d c o d e c v d d 1 2 m i c 0 _ p m i c 0 _ n m i c _ b i a s p a . 1 n o t e : t h e t h e r m a l p a d ( e p d ) s h o u l d b e c o n n e c t e d t o g n d .
n uc505 june 3 0 , 2016 page 20 of 130 rev 1.0 6 nuc505 series datasheet 4.2.4 numicro ? nuc505 yla2y qfn 48 - pin figure 4.2 - 4 numicro ? nuc505 yla2y qfn 48 - pin diagram n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 3 v d d x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t v s s v b a t r t c _ r p w r r t c _ n r w a k e p a . 8 p a . 9 p a . 1 0 p a . 1 1 v d d p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 5 p b . 6 p b . 7 u s b _ v b u s p b . 8 p b . 9 v s s a v d d a d c a v s s a d c p a . 0 p a . 1 p a . 2 p a . 3 p a . 4 v d d 1 2 p b . 1 0 p b . 1 1 p b . 1 2 v d d v d d l d o _ c a p v s s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 4 5 4 6 4 7 4 8 4 1 4 2 4 3 4 4 3 7 3 8 3 9 4 0 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 q f n 4 8 - p i n n o t e : t h e t h e r m a l p a d ( e p d ) s h o u l d b e c o n n e c t e d t o g n d .
n uc505 june 3 0 , 2016 page 21 of 130 rev 1.0 6 nuc505 series datasheet 4.2.5 numicro ? nuc505 dsa l qf p 64 - pin figure 4.2 - 5 numicro ? nuc505 dsa l qf p 64 - pin diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 6 1 6 2 6 3 6 4 5 7 5 8 5 9 6 0 5 3 5 4 5 5 5 6 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 3 1 4 1 5 1 6 4 9 5 0 5 1 5 2 3 2 3 1 3 0 2 9 3 6 3 5 3 4 3 3 l q f p 6 4 - p i n n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 3 p b . 1 4 p b . 1 5 p c . 0 v d d x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t v s s p a . 8 p a . 9 p a . 1 0 p a . 1 1 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 v d d p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 5 u s b _ v b u s a v d d c o d e c l h p o u t r h p o u t v s s v m i d a v d d h p a v s s h p a v d d a d c a v s s a d c p a . 0 p a . 1 p a . 2 p a . 3 p a . 4 v d d 1 2 p b . 1 0 p b . 1 1 p b . 1 2 v d d v d d l d o _ c a p v s s p c . 8 p c . 9 p c . 1 0 v d d 1 2 m i c 0 _ p m i c 0 _ n m i c _ b i a s p d . 4 p c . 1 1 p c . 1 2
n uc505 june 3 0 , 2016 page 22 of 130 rev 1.0 6 nuc505 series datasheet 4.2.6 numicro ? nuc505 ds13y lqfp 64 - pn figure 4.2 - 6 numicro ? nuc505 ds13y lqfp 64 - pin diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 6 1 6 2 6 3 6 4 5 7 5 8 5 9 6 0 5 3 5 4 5 5 5 6 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 3 1 4 1 5 1 6 4 9 5 0 5 1 5 2 3 2 3 1 3 0 2 9 3 6 3 5 3 4 3 3 l q f p 6 4 - p i n n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 3 p b . 1 4 p b . 1 5 p c . 0 v d d x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t v s s v b a t r t c _ r p w r r t c _ n r w a k e p a . 8 p a . 9 p a . 1 0 p a . 1 1 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 v d d p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 5 p b . 6 p b . 7 u s b _ v b u s p b . 8 p b . 9 a v d d c o d e c l h p o u t r h p o u t v s s v m i d a v d d h p a v s s h p a v d d a d c a v s s a d c p a . 0 p a . 1 p a . 2 p a . 3 p a . 4 p a . 5 p a . 6 p a . 7 v d d 1 2 p b . 1 0 p b . 1 1 p b . 1 2 v d d v d d l d o _ c a p v s s
n uc505 june 3 0 , 2016 page 23 of 130 rev 1.0 6 nuc505 series datasheet 4.2.7 numicro ? nuc505 yo13y qfn 88 - pin figure 4.2 - 7 numicro ? nuc505 yo13y qfn 88 - pin diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 8 5 8 6 8 7 8 8 8 1 8 2 8 3 8 4 7 7 7 8 7 9 8 0 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 3 1 4 1 5 1 6 7 3 7 4 7 5 7 6 3 8 3 7 3 6 3 5 4 8 4 7 4 6 4 5 q f n 8 8 - p i n 1 7 1 8 1 9 2 0 2 1 2 2 4 0 3 9 4 4 4 3 4 2 4 1 6 6 6 5 6 4 6 3 6 2 6 1 7 1 7 2 6 7 6 8 6 9 7 0 n r e s e t p d . 0 \ i c e _ c l k p d . 1 \ i c e _ d a t p b . 1 3 p b . 1 4 p b . 1 5 p c . 0 p c . 1 p c . 2 v d d p c . 3 p c . 4 p c . 5 p c . 6 v d d 1 2 x t 1 _ i n x t 1 _ o u t v d d 1 2 u s b _ d - u s b _ d + a v d d u s b u s b _ r e x t v b a t r t c _ r p w r r t c _ n r w a k e x 3 2 _ i n x 3 2 _ o u t p a . 8 p a . 9 p a . 1 0 p a . 1 1 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 7 p c . 8 p c . 8 p c . 1 0 v d d p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 5 p b . 6 p b . 7 u s b _ v b u s p b . 8 p b . 9 v d d a v d d h p l h p o u t v c m b f r h p o u t a v s s h p v m i d a v d d c o d e c v d d 1 2 m i c 0 _ p m i c 0 _ n m i c _ b i a s p d . 2 p d . 3 p d . 4 a v d d a d c a v s s a d c p a . 0 p a . 1 p a . 2 p a . 3 p a . 4 p a . 5 p a . 6 p a . 7 v d d 1 2 p b . 1 0 p b . 1 1 p b . 1 2 v d d p c . 1 1 p c . 1 2 p c . 1 3 p c . 1 4 v d d l d o _ c a p v s s n o t e : t h e t h e r m a l p a d ( e p d ) s h o u l d b e c o n n e c t e d t o g n d .
n uc505 june 3 0 , 2016 page 24 of 130 rev 1.0 6 nuc505 series datasheet pin description 4.3 4.3.1 numicro ? nuc505 dla lqfp 48 - pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp * description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i 2 c0 clock pin. 3 ice_dat i/o mfp0 serial wired debugger data pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i 2 c 0 data input/output pin. 4 pb . 14 i/o mfp0 general purpose digital i/o pin. u sbh1 _d + i/o mfp1 usb host - lite 1 differential signal d+. i2c1_ scl o mfp2 i2c 1 clock pin. 5 pb . 15 i/o mfp0 general purpose digital i/o pin. u sbh1 _d - i/o mfp1 usb host - lite 1 differential signal d - . i2c1_ sda i/o mfp2 i2c 1 data input/output pin. 6 v dd a mfp0 power supply for i / o ports , dc 3.3v. 7 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 8 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 9 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 10 u sb _d - a mfp0 usb differential signal d - . 11 u sb _d + a mfp0 usb differential signal d+. 12 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 13 u sb _rext a mfp0 12.1 k used internally for usb circuitry.
n uc505 june 3 0 , 2016 page 25 of 130 rev 1.0 6 nuc505 series datasheet 14 pa . 8 i/o mfp0 general purpose digital i/o pin. spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock. uart1_txd o mfp3 data transmitter output pin for uart1. 15 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m s erial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_rxd i mfp 3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 16 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin. i2c1_ scl o mfp2 i2c 1 clock pin. sd_clk o mfp4 sd /sd h mode - clock . syscfg[1] i mfp0 system configuration setting bit 1. 17 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd_cmd i mfp4 sd /sd h mode C command/response. 18 v dd a mfp0 power supply for i / o ports , dc 3.3v. 19 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd_d at 2 i/o mfp4 sd /sd h mode data line bit 2. 20 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. uart0_ rxd i mfp3 d ata receiver input pin for uart0 . sd_d at 3 i/o mfp4 sd /sd h mode data line bit 3.
n uc505 june 3 0 , 2016 page 26 of 130 rev 1.0 6 nuc505 series datasheet 21 pb . 2 i/o mfp0 general purpose digital i/o pin. spi 0 _ss o mfp1 spi 0 slave select pin. sd_cmd i mfp4 sd /sd h mode C command/response. 22 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd_clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 23 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 24 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. s d _ n cd i mfp4 sd /sd h mode C card detect. 25 u sb _ vbus i mfp0 power supply from usb host or hub. 26 v ss a mfp0 ground 27 av ddhp a mfp0 p ower supply for analog codec headphone, dc 3.3v. 28 lhpout a mfp0 headphone left channel output pin . 29 rhpout a mfp0 headphone right channel output pin . 30 av sshp a mfp0 g round for analog codec headphone. 31 vmid a mfp0 headphone reference power. 32 av ddcodec a mfp0 power supply for analog codec , dc 3.3v. 33 mic0 _ p a mfp0 microphone 0 positive input. 34 mic0 _ n a mfp0 microphone 0 negative input. 35 mic_bias a mfp0 codec left line - in channel or microphone bias. 36 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 37 pd . 4 i/o mfp0 general purpose digital i/o pin. rlinein a mfp1 codec right line - in channel .
n uc505 june 3 0 , 2016 page 27 of 130 rev 1.0 6 nuc505 series datasheet 3 8 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v. 39 a v ss adc a mfp0 g round pin for analog sar - adc. 40 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 41 pa . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input . 42 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin . 43 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 4 4 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 4 5 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 46 v dd a mfp0 power supply, dc 3.3v . 47 ldo_cap a mfp0 ldo output pin. 48 v ss a mfp0 ground.
n uc505 june 3 0 , 2016 page 28 of 130 rev 1.0 6 nuc505 series datasheet 4.3.2 numicro ? nuc505 dl13y lqfp 48 - pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp * description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i 2 c 0 clock pin. 3 ice_dat i/o mfp0 serial wired debugger data pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i 2 c 0 data input/output pin. 4 pb . 13 i/o mfp0 general purpose digital i/o pin. spi 1 _ miso i mfp1 spi 1 miso (master in, slave out) pin . u sbh 1 _d - i/o mfp2 usb host - lite 1 differential signal d - . uart2_n rts o mfp3 request to send output pin for uart2 . pwm _ch3 i/o mfp4 pwm channel3 output/capture input. 5 v dd a mfp0 power supply for i / o ports , dc 3.3v. 6 v ss a mfp0 ground . 7 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 8 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 9 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 10 u sb _d - a mfp0 usb differential signal d - . 11 u sb _d + a mfp0 usb differential signal d+. 12 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 13 u sb _rext a mfp0 12.1 k used internally for usb circuitry. 14 v bat a mfp0 p ower supply by batteries for rtc, dc 3.3v.
n uc505 june 3 0 , 2016 page 29 of 130 rev 1.0 6 nuc505 series datasheet 15 rtc_rpwr o mfp0 enable external power control source when active high . 16 rtc_ n rwake i mfp0 system power enable trigger when active low. 17 pa . 8 i/o mfp0 general purpose digital i/o pin. spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock. uart1_ txd o mfp3 data transmitter output pin for uart1 . 18 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m s erial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_ rxd i mfp 3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 19 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin. i2c1_ scl o mfp2 i2c 1 clock pin. sd _clk o mfp4 sd /sd h mode - clock . syscfg[1] i mfp0 system configuration setting bit 1. 20 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd _cmd i mfp4 sd /sd h mode C command/response. 21 v dd a mfp0 power supply for i / o ports , dc 3.3v. 22 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd_d at 2 i/o mfp4 sd /sd h mode data line bit 2. 23 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin.
n uc505 june 3 0 , 2016 page 30 of 130 rev 1.0 6 nuc505 series datasheet uart0_ rxd i mfp3 d ata receiver input pin for uart0 . sd _d at 3 i/o mfp4 sd /sd h mode data line bit 3. 24 pb . 2 i/o mfp0 general purpose digital i/o pin. spi 0 _ss o mfp1 spi 0 slave select pin. sd _cmd i mfp4 sd /sd h mode C command/response. 25 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd _clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 26 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 27 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. s d _ n cd i mfp4 sd /sd h mode C card detect. 28 pb . 6 i/o mfp0 general purpose digital i/o pin. uart1_ txd o mfp3 data transmitter output pin for uart1. sd _d at 0 i/o mfp4 sd /sd h mode data line bit 0. 29 pb . 7 i/o mfp0 general purpose digital i/o pin. uart1_ rxd i mfp3 d ata receiver input pin for uart1 . sd _d at 1 i/o mfp4 sd /sd h mode data line bit 1. 30 u sb _ vbus i mfp0 power supply from usb host or hub. 3 1 pb . 8 i/o mfp0 general purpose digital i/o pin. usb h _pwen o mfp1 usb host mode to control an external overcurrent source . tm1_ cnt_out i /o mfp2 timer1 event counter input/toggle output. uart1_n cts i mfp3 clear to send input pin for uart1 . sd _d at 2 i/o mfp4 sd /sd h mode data line bit 2.
n uc505 june 3 0 , 2016 page 31 of 130 rev 1.0 6 nuc505 series datasheet 3 2 pb . 9 i/o mfp0 general purpose digital i/o pin. usbh_ovd i mfp1 usb host bus power over voltage detector . tm1_ ext i mfp2 timer 1 external capture input. uart1_n rts o mfp3 request to send output pin for uart1. sd _d at 3 i/o mfp4 sd /sd h mode data line bit 3. 3 3 v ss a mfp0 ground 3 4 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v. 3 5 a v ss adc a mfp0 g round pin for analog sar - adc. 3 6 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 3 7 pa . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input . 3 8 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin . 39 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 4 0 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 41 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 42 pb . 10 i/o mfp0 general purpose digital i/o pin. spi 1 _ss o mfp1 spi 1 slave select pin. i2c1_ scl o mfp2 i2c 1 clock pin. uart2_ txd o mfp3 data transmitter output pin for uart2. pwm _ch0 i/ o mfp4 pwm channel0 output/capture input.
n uc505 june 3 0 , 2016 page 32 of 130 rev 1.0 6 nuc505 series datasheet 43 pb . 11 i/o mfp0 general purpose digital i/o pin. spi 1 _clk o mfp1 spi 1 serial clock pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. uart2_ rxd i mfp3 d ata receiver input pin for uart2 . pwm _ch1 i/ o mfp4 pwm channel1 output/capture input . 44 pb . 12 i/o mfp0 general purpose digital i/o pin. spi 1 _ mosi o mfp1 spi 1 mosi (master out, slave in) pin. u sbh 1 _d + i/o mfp2 usb host - lite 1 differential signal d+ uart2_n cts i mfp3 clear to s end input pin for uart2 . pwm _ch2 i/ o mfp4 pwm channel2 output/capture input. 45 v dd a mfp0 power supply for i / o ports , dc 3.3v. 46 v dd a mfp0 power supply , dc 3.3v . 47 ldo_cap a mfp0 ldo output pin. 48 v ss a mfp0 ground.
n uc505 june 3 0 , 2016 page 33 of 130 rev 1.0 6 nuc505 series datasheet 4.3.3 numicro ? nuc505 yla qf n 48 - pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp * description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i 2 c0 clock pin. 3 ice_dat i/o mfp0 serial wired debugger data pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i 2 c 0 data input/output pin. 4 pb . 14 i/o mfp0 general purpose digital i/o pin. u sbh1 _d + i/o mfp1 usb host - lite 1 differential signal d+. i2c1_ scl o mfp2 i2c 1 clock pin. 5 pb . 15 i/o mfp0 general purpose digital i/o pin. u sbh1 _d - i/o mfp1 usb host - lite 1 differential signal d - . i2c1_ sda i/o mfp2 i2c 1 data input/output pin. 6 v dd a mfp0 power supply for i / o ports , dc 3.3v. 7 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 8 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 9 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 10 u sb _d - a mfp0 usb differential signal d - . 11 u sb _d + a mfp0 usb differential signal d+. 12 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 13 u sb _rext a mfp0 12.1 k used internally for usb circuitry. 14 pa . 8 i/o mfp0 general purpose digital i/o pin.
n uc505 june 3 0 , 2016 page 34 of 130 rev 1.0 6 nuc505 series datasheet spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock. uart1_txd o mfp3 data transmitter output pin for uart1. 15 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m s erial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_rxd i mfp 3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 16 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin. i2c1_ scl o mfp2 i2c 1 clock pin. sd_clk o mfp4 sd /sd h mode - clock . syscfg[1] i mfp0 system configuration setting bit 1. 17 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd_cmd i mfp4 sd /sd h mode C command/response. 18 v dd a mfp0 power supply for i / o ports , dc 3.3v. 19 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd_d at 2 i/o mfp4 sd /sd h mode data line bit 2. 20 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. uart0_ rxd i mfp3 d ata receiver input pin for uart0 . sd_d at 3 i/o mfp4 sd /sd h mode data line bit 3. 21 pb . 2 i/o mfp0 general purpose digital i/o pin.
n uc505 june 3 0 , 2016 page 35 of 130 rev 1.0 6 nuc505 series datasheet spi 0 _ss o mfp1 spi 0 slave select pin. sd_cmd i mfp4 sd /sd h mode C command/response. 22 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd_clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 23 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 24 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. s d _ n cd i mfp4 sd /sd h mode C card detect. 25 u sb _ vbus i mfp0 power supply from usb host or hub. 26 v ss a mfp0 ground 27 av ddhp a mfp0 p ower supply for analog codec headphone, dc 3.3v. 28 lhpout a mfp0 headphone left channel output pin . 29 rhpout a mfp0 headphone right channel output pin . 30 av sshp a mfp0 g round for analog codec headphone. 31 vmid a mfp0 headphone reference power. 32 av ddcodec a mfp0 power supply for analog codec , dc 3.3v. 33 mic0 _ p a mfp0 microphone 0 positive input. 34 mic0 _ n a mfp0 microphone 0 negative input. 35 mic_bias a mfp0 codec left line - in channel or microphone bias. 36 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 37 pd . 4 i/o mfp0 general purpose digital i/o pin. rlinein a mfp1 codec right line - in channel . 3 8 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v.
n uc505 june 3 0 , 2016 page 36 of 130 rev 1.0 6 nuc505 series datasheet 39 a v ss adc a mfp0 g round pin for analog sar - adc. 40 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 41 pa . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input . 42 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin . 43 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 4 4 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 4 5 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 46 v dd a mfp0 power supply, dc 3.3v . 47 ldo_cap a mfp0 ldo output pin. 48 v ss a mfp0 ground. note: the thermal pad (epd) on the bottom of qfn package should be connected to gnd.
n uc505 june 3 0 , 2016 page 37 of 130 rev 1.0 6 nuc505 series datasheet 4.3.4 numicro ? nuc505 yla2y qfn 48 - pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp * description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i 2 c0 clock pin. 3 ice_dat i/o mfp0 serial wired debugger data pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i 2 c 0 data input/output pin. 4 pb . 13 i/o mfp0 general purpose digital i/o pin. spi 1 _ miso i mfp1 spi 1 miso (master in, slave out) pin . u sbh1 _d - i/o mfp2 usb host - lite 1 differential signal d - . uart2_n rts o mfp3 request to send output pin for uart2 . pwm _ch3 i/o mfp4 pwm channel3 output/capture input. 5 v dd a mfp0 power supply for i / o ports , dc 3.3v. 6 v ss a mfp0 ground . 7 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 8 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 9 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 10 u sb _d - a mfp0 usb differential signal d - . 11 u sb _d + a mfp0 usb differential signal d+. 12 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 13 u sb _rext a mfp0 12.1 k used internally for usb circuitry. 14 v bat a mfp0 p ower supply by batteries for rtc, dc 3.3v.
n uc505 june 3 0 , 2016 page 38 of 130 rev 1.0 6 nuc505 series datasheet 15 rtc_rpwr o mfp0 enable external power control source when active high . 16 rtc_ n rwake i mfp0 system power enable trigger when active low. 17 pa . 8 i/o mfp0 general purpose digital i/o pin. spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock. uart1_txd o mfp3 data transmitter output pin for uart1. 18 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m s erial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_rxd i mfp 3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 19 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin. i2c1_ scl o mfp2 i2c 1 clock pin. sd_clk o mfp4 sd /sd h mode - clock . syscfg[1] i mfp0 system configuration setting bit 1. 20 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd_cmd i mfp4 sd /sd h mode C command/response. 21 v dd a mfp0 power supply for i / o ports , dc 3.3v. 22 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd_d at 2 i/o mfp4 sd /sd h mode data line bit 2. 23 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin.
n uc505 june 3 0 , 2016 page 39 of 130 rev 1.0 6 nuc505 series datasheet uart0_ rxd i mfp3 d ata receiver input pin for uart0 . sd_d at 3 i/o mfp4 sd /sd h mode data line bit 3. 24 pb . 2 i/o mfp0 general purpose digital i/o pin. spi 0 _ss o mfp1 spi 0 slave select pin. sd_cmd i mfp4 sd /sd h mode C command/response. 25 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd_clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 26 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 27 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. s d _ n cd i mfp4 sd /sd h mode C card detect. 28 pb . 6 i/o mfp0 general purpose digital i/o pin. uart1_ txd o mfp3 data transmitter output pin for uart1. sd_d at 0 i/o mfp4 sd /sd h mode data line bit 0. 29 pb . 7 i/o mfp0 general purpose digital i/o pin. uart1_ rxd i mfp3 d ata receiver input pin for uart1 . sd_d at 1 i/o mfp4 sd /sd h mode data line bit 1. 30 u sb _ vbus i mfp0 power supply from usb host or hub. 3 1 pb . 8 i/o mfp0 general purpose digital i/o pin. usbh_pwen o mfp1 usb host mode to control an external overcurrent source . tm1_ cnt_out i /o mfp2 timer1 event counter input/toggle output. uart1_n cts i mfp3 clear to send input pin for uart1 . sd_d at 2 i/o mfp4 sd /sd h mode data line bit 2.
n uc505 june 3 0 , 2016 page 40 of 130 rev 1.0 6 nuc505 series datasheet 3 2 pb . 9 i/o mfp0 general purpose digital i/o pin. usbh_ovd i mfp1 usb host bus power over voltage detector . tm1_ ext i mfp2 timer 1 external capture input. uart1_n rts o mfp3 request to send output pin for uart1. sd_d at 3 i/o mfp4 sd /sd h mode data line bit 3. 3 3 v ss a mfp0 ground 3 4 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v. 3 5 a v ss adc a mfp0 g round pin for analog sar - adc. 3 6 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 3 7 pa . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input . 3 8 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin . 39 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 4 0 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 41 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 42 pb . 10 i/o mfp0 general purpose digital i/o pin. spi 1 _ss o mfp1 spi 1 slave select pin. i2c1_ scl o mfp2 i2c 1 clock pin. uart2_ txd o mfp3 data transmitter output pin for uart2. pwm _ch0 i/ o mfp4 pwm channel0 output/capture input.
n uc505 june 3 0 , 2016 page 41 of 130 rev 1.0 6 nuc505 series datasheet 43 pb . 11 i/o mfp0 general purpose digital i/o pin. spi 1 _clk o mfp1 spi 1 serial clock pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. uart2_ rxd i mfp3 d ata receiver input pin for uart2 . pwm _ch1 i/ o mfp4 pwm channel1 output/capture input . 44 pb . 12 i/o mfp0 general purpose digital i/o pin. spi 1 _ mosi o mfp1 spi 1 mosi (master out, slave in) pin. u sbh1 _d + i/o mfp2 usb host - lite 1 differential signal d+ uart2_n cts i mfp3 clear to s end input pin for uart2 . pwm _ch2 i/ o mfp4 pwm channel2 output/capture input. 45 v dd a mfp0 power supply for i / o ports , dc 3.3v. 46 v dd a mfp0 power supply, dc 3.3v . 47 ldo_cap a mfp0 ldo output pin. 48 v ss a mfp0 ground. note: the thermal pad (epd) on the bottom of qfn package should be connected to gnd.
n uc505 june 3 0 , 2016 page 42 of 130 rev 1.0 6 nuc505 series datasheet 4.3.5 numicro ? nuc505 dsa lqfp 64 - pin description mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. 3 ice_dat i/o mfp0 serial w ired d ebugger d ata pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. 4 pb . 13 i/o mfp0 general purpose digital i/o pin. spi 1 _ miso i mfp1 spi 1 miso (master in, slave out) pin . u sbh1 _d - i/o mfp2 usb host - lite 1 differential signal d - . uart2_n rts o mfp3 request to send output pin for uart2 . pwm _ch3 i/ o mfp4 pwm channel3 output/capture input. 5 pb . 14 i/o mfp0 general purpose digital i/o pin. u sbh1 _d + i/o mfp1 usb host - lite 1 differential signal d+. i2c1_ scl o mfp2 i2c 1 clock pin. 6 pb . 15 i/o mfp0 general purpose digital i/o pin. u sbh1 _d - i/o mfp1 usb host - lite 1 differential signal d - . i2c1_ sda i/o mfp2 i2c 1 data input/output pin. 7 pc . 0 i/o mfp0 general purpose digital i/o pin. sd_cmd i mfp1 sd /sd h mode C command/response. 8 v dd a mfp0 power supply for i / o ports , dc 3.3v. 9 v ss a mfp0 ground
n uc505 june 3 0 , 2016 page 43 of 130 rev 1.0 6 nuc505 series datasheet 1 0 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 11 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 12 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 13 u sb _d - a mfp0 usb differential signal d - . 14 u sb _d + a mfp0 usb differential signal d+. 15 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 16 u sb _rext a mfp0 12.1 k used internally for usb circuitry. 17 pa . 8 i/o mfp0 general purpose digital i/o pin. spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock. uart1_txd o mfp3 data transmitter output pin for uart1. 18 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m serial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_rxd i mfp3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 19 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin . ( data 0 pin for quad m ode i/o ). i2c1_ scl o mfp2 i2c 1 clock pin. sd_clk o mfp4 sd /sd h mode C clock. syscfg[1] i mfp0 system configuration setting bit 1. 2 0 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin . ( data 1 pin for quad m ode i/o ). i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd_cmd i mfp4 sd /sd h mode C command/response. 2 1 pa . 12 i/o mfp0 general purpose digital i/o pin.
n uc505 june 3 0 , 2016 page 44 of 130 rev 1.0 6 nuc505 series datasheet spi m _d2 i/o mfp1 spi m data 2 pin for quad m ode i/o . tm0_cnt_out i mfp2 timer0 event counter input/toggle output. 2 2 pa . 13 i/o mfp0 general purpose digital i/o pin. spi m _d3 i/o mfp1 spi m data 3 pin for quad m ode i/o . tm0_ext i mfp2 timer0 external capture input. sd_ n cd i mfp4 sd /sd h mode C card detect. 2 3 pa . 14 i/o mfp0 general purpose digital i/o pin. i2c0_scl o mfp2 i2c 0 clock pin. sd_d at 0 i/o mfp4 sd /sd h mode data line bit 0. 2 4 pa . 15 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. sd_d at 1 i/o mfp4 sd /sd h mode data line bit 1. 25 pc . 8 i/o mfp0 general purpose digital i/o pin. i2s_mclk o mfp1 i 2 s master clock output pin. 26 pc . 9 i/o mfp0 general purpose digital i/o pin. i2s_di i mfp1 i 2 s data input. tm2_cnt_out i/o mfp2 timer2 event counter input/toggle output. pwm _ch0 i/ o mfp3 pwm channel0 output/capture input. 27 pc . 10 i/o mfp0 general purpose digital i/o pin. i2s_do o mfp1 i 2 s data output. tm2_ext i mfp2 timer2 external capture input. pwm _ch1 i/ o mfp3 pwm channel1 output/capture input. 28 v dd a mfp0 power supply for i / o ports , dc 3.3v. 29 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd_d at 2 i/o mfp4 sd /sd h mode data line bit 2.
n uc505 june 3 0 , 2016 page 45 of 130 rev 1.0 6 nuc505 series datasheet 30 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. uart0_ rxd i mfp3 d ata receiver input pin for uart0 . sd_d at 3 i/o mfp4 sd /sd h mode data line bit 3. 31 pb . 2 i/o mfp0 general purpose digital i/o pin. spi 0 _ss o mfp1 spi 0 slave select pin. sd_cmd i mfp4 sd /sd h mode C command/response. 32 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd_clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 33 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 34 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. sd_ n cd i mfp4 sd /sd h mode C card detect. 35 u sb _ vbus i mfp0 power supply from usb host or hub. 36 v ss a mfp0 ground. 37 av ddhp ap vdd p ower supply for analog codec headphone, dc 3.3v. 38 lhpout a mfp0 headphone left channel output pin . 39 rhpout a mfp0 headphone right channel output pin . 40 av sshp a mfp0 g round for analog codec headphone. 41 vmid a mfp0 headphone reference power. 42 av dd codec a mfp0 p ower supply for analog codec , dc 3.3v. 43 mic0 _ p a mfp0 microphone 0 positive input. 44 mic0 _ n a mfp0 microphone 0 negative input.
n uc505 june 3 0 , 2016 page 46 of 130 rev 1.0 6 nuc505 series datasheet 45 mic_bias a mfp0 codec left line - in channel or microphone bias. 46 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 47 pd . 4 i/o mfp0 general purpose digital i/o pin. rlinein a mfp1 codec right line - in channel . 48 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v. 49 a v ss adc a mfp0 g round pin for analog sar - adc. 50 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 5 1 p a . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input . 5 2 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin. 5 3 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 5 4 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 5 5 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 56 pb . 10 i/o mfp0 general purpose digital i/o pin. spi 1 _ss o mfp1 spi 1 slave select pin. i2c1_ scl o mfp2 i2c 1 clock pin. uart2_ txd o mfp3 data transmitter output pin for uart2. pwm _ch0 i/ o mfp4 pwm channel0 output/capture input. 57 pb . 11 i/o mfp0 general purpose digital i/o pin. spi 1 _clk o mfp1 spi 1 serial clock pin.
n uc505 june 3 0 , 2016 page 47 of 130 rev 1.0 6 nuc505 series datasheet i2c1_ sda i/o mfp2 i2c 1 data input/output pin. uart2_ rxd i mfp3 d ata receiver input pin for uart2 . pwm _ch1 i/ o mfp4 pwm channel1 output/capture input. 58 pb . 12 i/o mfp0 general purpose digital i/o pin. spi 1 _ mosi o mfp1 spi 1 mosi (master out, slave in) pin. u sbh1 _d + i/o mfp2 usb host - lite 1 differential signal d+ uart2_n cts i mfp3 clear to send input pin for uart2 . pwm _ch2 i/ o mfp4 pwm channel2 output/capture input. 59 v dd a mfp0 power supply for i / o ports , dc 3.3v. 60 pc . 11 i/o mfp0 general purpose digital i/o pin. i2s_lrclk i/ o mfp1 i 2 s left right channel clock. tm3_cnt_out i/o mfp2 timer3 event counter input/toggle output. pwm _ch2 i/ o mfp3 pwm channel2 output/capture input. 61 pc . 12 i/o mfp0 general purpose digital i/o pin. i2s_bclk i/ o mfp1 i 2 s bit clock pin. tm3_ext i mfp2 timer3 external capture input. pwm _ch3 i/o mfp3 pwm channel3 output/capture input. 62 v dd a mfp0 power supply, dc 3.3v. 63 ldo_cap a mfp0 ldo output pin. 64 v ss a mfp0 ground.
n uc505 june 3 0 , 2016 page 48 of 130 rev 1.0 6 nuc505 series datasheet 4.3.6 numicro ? nuc505 ds13y lqfp 64 - pin description mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. 3 ice_dat i/o mfp0 serial w ired d ebugger d ata pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. 4 pb . 13 i/o mfp0 general purpose digital i/o pin. spi 1 _ miso i mfp1 spi 1 miso (master in, slave out) pin . u sbh 1 _d - i/o mfp2 usb host - lite 1 differential signal d - . uart2_n rts o mfp3 request to send output pin for uart2 . pwm _ch3 i/ o mfp4 pwm channel3 output/capture input. 5 pb . 14 i/o mfp0 general purpose digital i/o pin. u sbh 1 _d + i/o mfp1 usb host - lite 1 differential signal d+. i2c1_ scl o mfp2 i2c 1 clock pin. 6 pb . 15 i/o mfp0 general purpose digital i/o pin. u sbh 1 _d - i/o mfp1 usb host - lite 1 differential signal d - . i2c1_ sda i/o mfp2 i2c 1 data input/output pin. 7 pc . 0 i/o mfp0 general purpose digital i/o pin. sd _cmd i mfp1 sd /sd h mode C command/response. 8 v dd a mfp0 power supply for i / o ports , dc 3.3v. 9 v ss a mfp0 ground
n uc505 june 3 0 , 2016 page 49 of 130 rev 1.0 6 nuc505 series datasheet 1 0 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 11 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 12 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 13 u sb _d - a mfp0 usb differential signal d - . 14 u sb _d + a mfp0 usb differential signal d+. 15 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 16 u sb _rext a mfp0 12.1 k used internally for usb circuitry. 17 v bat a mfp0 p ower supply by batteries for rtc, dc 3.3v. 18 rtc_rpwr o mfp0 enable external power control source when active high . 19 rtc_ n rwake i mfp0 system power enable trigger when active low. 20 pa . 8 i/o mfp0 general purpose digital i/o pin. spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock. uart1_ txd o mfp3 data transmitter output pin for uart1. 21 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m serial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_ rxd i mfp3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 22 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin . ( data 0 pin for quad m ode i/o ). i2c1_ scl o mfp2 i2c 1 clock pin. sd _clk o mfp4 sd /sd h mode C clock. syscfg[1] i mfp0 system configuration setting bit 1. 23 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin . ( data 1 pin for quad m ode i/o ).
n uc505 june 3 0 , 2016 page 50 of 130 rev 1.0 6 nuc505 series datasheet i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd _cmd i mfp4 sd /sd h mode C command/response. 24 pa . 12 i/o mfp0 general purpose digital i/o pin. spi m _d2 i/o mfp1 spi m data 2 pin for quad m ode i/o . tm0_cnt_out i mfp2 timer0 event counter input/toggle output. 25 pa . 13 i/o mfp0 general purpose digital i/o pin. spi m _d3 i/o mfp1 spi m data 3 pin for quad m ode i/o . tm0_ext i mfp2 timer0 external capture input. sd _ n cd i mfp4 sd /sd h mode C card detect. 26 pa . 14 i/o mfp0 general purpose digital i/o pin. i2c0_scl o mfp2 i2c 0 clock pin. sd _d at 0 i/o mfp4 sd /sd h mode data line bit 0. 27 pa . 15 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. sd _d at 1 i/o mfp4 sd /sd h mode data line bit 1. 28 v dd a mfp0 power supply for i / o ports , dc 3.3v. 29 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd _d at 2 i/o mfp4 sd /sd h mode data line bit 2. 30 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. uart0_ rxd i mfp3 d ata receiver input pin for uart0 . sd _d at 3 i/o mfp4 sd /sd h mode data line bit 3. 31 pb . 2 i/o mfp0 general purpose digital i/o pin. spi 0 _ss o mfp1 spi 0 slave select pin. sd _cmd i mfp4 sd /sd h mode C command/response.
n uc505 june 3 0 , 2016 page 51 of 130 rev 1.0 6 nuc505 series datasheet 32 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd _clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 33 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 34 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. sd _ n cd i mfp4 sd /sd h mode C card detect. 35 pb . 6 i/o mfp0 general purpose digital i/o pin. uart1_ txd o mfp3 data transmitter output pin for uart1. sd _d at 0 i/o mfp4 sd /sd h mode data line bit 0. 36 pb . 7 i/o mfp0 general purpose digital i/o pin. uart1_ rxd i mfp3 d ata receiver input pin for uart1 . sd _d at 1 i/o mfp4 sd /sd h mode data line bit 1. 37 u sb _ vbus i mfp0 power supply from usb host or hub. 38 pb . 8 i/o mfp0 general purpose digital i/o pin. usb h _pwen o mfp1 usb host mode to control an external overcurrent source . tm1_cnt_out i /o mfp2 timer1 event counter input/toggle output. uart1_n cts i mfp3 clear to send input pin for uart1 . sd _d at 2 i/o mfp4 sd /sd h mode data line bit 2. 39 pb . 9 i/o mfp0 general purpose digital i/o pin. usbh_ovd i mfp1 usb host bus power over voltage detector . tm1_ext i mfp2 timer1 external capture input. uart1_n rts o mfp3 request to send output pin for uart1. sd _d at 3 i/o mfp4 sd /sd h mode data line bit 3.
n uc505 june 3 0 , 2016 page 52 of 130 rev 1.0 6 nuc505 series datasheet 40 v ss a mfp0 ground. 4 1 av ddhp ap vdd p ower supply for analog codec headphone, dc 3.3v. 4 2 lhpout a mfp0 headphone left channel output pin . 4 3 rhpout a mfp0 headphone right channel output pin . 4 4 av sshp a mfp0 g round for analog codec headphone. 4 5 vmid a mfp0 headphone reference power. 4 6 av dd codec a mfp0 p ower supply for analog codec , dc 3.3v. 4 7 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v. 4 8 a v ss adc a mfp0 g round pin for analog sar - adc. 49 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 5 0 p a . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input . 5 1 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin. 5 2 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 5 3 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 5 4 pa . 5 i/o mfp0 general purpose digital i/o pin. adc _ch 5 a mfp1 adc channel 5 analog input . 5 5 pa . 6 i/o mfp0 general purpose digital i/o pin. adc _ch 6 a mfp1 adc channel 6 analog input . 5 6 pa . 7 i/o mfp0 general purpose digital i/o pin.
n uc505 june 3 0 , 2016 page 53 of 130 rev 1.0 6 nuc505 series datasheet adc _ch 7 a mfp1 adc channel 7 analog input . 57 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 58 pb . 10 i/o mfp0 general purpose digital i/o pin. spi 1 _ss o mfp1 spi 1 slave select pin. i2c1_ scl o mfp2 i2c 1 clock pin. uart2_ txd o mfp3 data transmitter output pin for uart2. pwm _ch0 i/ o mfp4 pwm channel0 output/capture input. 59 pb . 11 i/o mfp0 general purpose digital i/o pin. spi 1 _clk o mfp1 spi 1 serial clock pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. uart2_ rxd i mfp3 d ata receiver input pin for uart2 . pwm _ch1 i/ o mfp4 pwm channel1 output/capture input. 60 pb . 12 i/o mfp0 general purpose digital i/o pin. spi 1 _ mosi o mfp1 spi 1 mosi (master out, slave in) pin. u sbh 1 _d + i/o mfp2 usb host - lite 1 differential signal d+ uart2_n cts i mfp3 clear to send input pin for uart2 . pwm _ch2 i/ o mfp4 pwm channel2 output/capture input. 61 v dd a mfp0 power supply for i / o ports , dc 3.3v. 62 v dd a mfp0 power supply , dc 3.3v . 63 ldo_cap a mfp0 ldo output pin. 64 v ss a mfp0 ground.
n uc505 june 3 0 , 2016 page 54 of 130 rev 1.0 6 nuc505 series datasheet 4.3.7 numicro ? nuc505 yo13y qfn 88 - pin description mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. pin no . pin name type mfp description 1 n reset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 2 ice_clk o mfp0 serial wired debugger clock pin. (in ice mode) pd . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. 3 ice_dat i/o mfp0 serial w ired d ebugger d ata pin. (in ice mode) pd . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. 4 pb . 13 i/o mfp0 general purpose digital i/o pin. spi 1 _ miso i mfp1 spi 1 miso (master in, slave out) pin. u sbh 1 _d - i/o mfp2 usb host - lite 1 differential signal d - . uart2_n rts o mfp3 request to send output pin for uart2 . pwm _ch3 i/ o mfp4 pwm channel3 output/capture input. 5 pb . 14 i/o mfp0 general purpose digital i/o pin. u sbh 1 _d + i/o mfp1 usb host - lite 1 differential signal d+. i2c1_ scl o mfp2 i2c 1 clock pin. 6 pb . 15 i/o mfp0 general purpose digital i/o pin. u sbh 1 _d - i/o mfp1 usb host - lite 1 differential signal d - . i2c1_ sda i/o mfp2 i2c 1 data input/output pin. 7 pc . 0 i/o mfp0 general purpose digital i/o pin. sd _cmd i mfp1 sd /sd h mode C command/response. 8 pc . 1 i/o mfp0 general purpose digital i/o pin. sd _clk o mfp1 sd /sd h mode C clock.
n uc505 june 3 0 , 2016 page 55 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description 9 pc . 2 i/o mfp0 general purpose digital i/o pin. sd _ n cd i mfp1 sd /sd h mode C card detect. 1 0 v dd a mfp0 power supply for i / o ports , dc 3.3v. 1 1 pc . 3 i/o mfp0 general purpose digital i/o pin. 1 2 pc . 4 i/o mfp0 general purpose digital i/o pin. sd _d at 0 i/o mfp1 sd /sd h mode data line bit 0. 1 3 pc . 5 i/o mfp0 general purpose digital i/o pin. sd _d at 1 i/o mfp1 sd /sd h mode data line bit 1. 1 4 pc . 6 i/o mfp0 general purpose digital i/o pin. sd _d at 2 i/o mfp1 sd /sd h mode data line bit 2. 1 5 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 1 6 x t1_in i mfp0 external 12 mhz (high speed) crystal input pin. 17 x t1_out o mfp0 external 12 mhz (high speed) crystal output pin. 18 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 19 u sb _d - a mfp0 usb differential signal d - . 20 u sb _d + a mfp0 usb differential signal d+. 21 a v dd usb a mfp0 p ower supply for analog usb, dc 3.3v. 22 u sb _rext a mfp0 12.1 k used internally for usb circuitry. 23 v bat a mfp0 p ower supply by batteries for rtc, dc 3.3v. 24 rtc_rpwr o mfp0 enable external power control source when active high . 25 rtc_ n rwake i mfp0 system power enable trigger when active low. 26 x32_in i mfp0 external 32.768 khz (low speed) crystal input pin. 27 x32_out o mfp0 external 32.768 khz (low speed) crystal output pin. 28 pa . 8 i/o mfp0 general purpose digital i/o pin. spi m _ss o mfp1 spi m slave select pin . i2s_lrclk i/ o mfp2 i 2 s left right channel clock.
n uc505 june 3 0 , 2016 page 56 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description uart1_ txd o mfp3 data transmitter output pin for uart1. 29 pa . 9 i/o mfp0 general purpose digital i/o pin. spi m _clk o mfp1 spi m serial clock pin . i2s_bclk i/ o mfp2 i 2 s bit clock pin . uart1_ rxd i mfp3 d ata receiver input pin for uart1 . syscfg[0] i mfp0 system configuration setting bit 0. 30 pa . 10 i/o mfp0 general purpose digital i/o pin. spi m _ mosi i/o mfp1 spi m mosi (master out, slave in) pin . ( data 0 pin for quad m ode i/o ). i2c1_ scl o mfp2 i2c 1 clock pin. sd _clk o mfp4 sd /sd h mode C clock. syscfg[1] i mfp0 system configuration setting bit 1. 31 pa . 11 i/o mfp0 general purpose digital i/o pin. spi m _ miso i/o mfp1 spi m miso (master in, slave out) pin . ( data 1 pin for quad m ode i/o ). i2c1_ sda i/o mfp2 i2c 1 data input/output pin. sd _cmd i mfp4 sd /sd h mode C command/response. 32 pa . 12 i/o mfp0 general purpose digital i/o pin. spi m _d2 i/o mfp1 sp im data 2 pin for quad m ode i/o . tm0_cnt_out i /o mfp2 timer0 event counter input/toggle output. 33 pa . 13 i/o mfp0 general purpose digital i/o pin. spi m _d3 i/o mfp1 spi m data 3 pin for quad m ode i/o . tm0_ext i mfp2 timer0 external capture input. sd _ n cd i mfp4 sd /sd h mode C card detect. 34 pa . 14 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. sd _d at 0 i/o mfp4 sd /sd h mode data line bit 0.
n uc505 june 3 0 , 2016 page 57 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description 35 pa . 15 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o mfp2 i2c 0 data input/output pin. sd _d at 1 i/o mfp4 sd /sd h mode data line bit 1. 36 pc . 7 i/o mfp0 general purpose digital i/o pin. sd _d at 3 i/o mfp1 sd /sd h mode data line bit 3. 37 pc . 8 i/o mfp0 general purpose digital i/o pin. i2s_mclk o mfp1 i 2 s master clock output pin. 38 pc . 9 i/o mfp0 general purpose digital i/o pin. i2s_di i mfp1 i 2 s data input. tm2_cnt_out i/o mfp2 timer2 event counter input/toggle output. pwm _ch0 i/ o mfp3 pwm channel0 output/capture input. 39 pc . 10 i/o mfp0 general purpose digital i/o pin. i2s_do o mfp1 i 2 s data output. tm2_ext i mfp2 timer2 external capture input. pwm _ch1 i/ o mfp3 pwm channel1 output/capture input. 40 v dd a mfp0 power supply for i / o ports , dc 3.3v. 41 pb . 0 i/o mfp0 general purpose digital i/o pin. i2c0_ scl o mfp2 i2c 0 clock pin. uart0_ txd o mfp3 data transmitter output pin for uart0. sd _d at 2 i/o mfp4 sd /sd h mode data line bit 2. 42 pb . 1 i/o mfp0 general purpose digital i/o pin. i2c0_ sda i/o fmp2 i2c 0 data input/output pin. uart0_ rxd i fmp3 d ata receiver input pin for uart0 . sd _d at 3 i/o mfp4 sd /sd h mode data line bit 3. 43 pb . 2 i/o mfp0 general purpose digital i/o pin. spi 0 _ss o mfp1 spi 0 slave select pin.
n uc505 june 3 0 , 2016 page 58 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description sd _cmd i mfp4 sd /sd h mode C command/response. 44 pb . 3 i/o mfp0 general purpose digital i/o pin. spi 0 _clk o mfp1 spi 0 serial clock pin. sd _clk o mfp4 sd /sd h mode C clock. syscfg[2] i mfp0 system configuration setting bit 2. 45 pb . 4 i/o mfp0 general purpose digital i/o pin. spi 0 _ mosi o mfp1 spi 0 mosi (master out, slave in) pin. syscfg[3] i mfp0 system configuration setting bit 3. 46 pb . 5 i/o mfp0 general purpose digital i/o pin. spi 0 _ miso i mfp1 spi 0 miso (master in, slave out) pin. sd _ n cd i mfp4 sd /sd h mode C card detect. 47 pb . 6 i/o mfp0 general purpose digital i/o pin. uart1_ txd o mfp3 data transmitter output pin for uart1. sd _d at 0 i/o mfp4 sd /sd h mode data line bit 0. 48 pb . 7 i/o mfp0 general purpose digital i/o pin. uart1_ rxd i mfp3 d ata receiver input pin for uart1 . sd _d at 1 i/o mfp4 sd /sd h mode data line bit 1. 49 u sb _ vbus i mfp0 power supply from usb host or hub. 5 0 pb . 8 i/o mfp0 general purpose digital i/o pin. usb h _pwen o mfp1 usb host mode to control an external overcurrent source . tm1_cnt_out i /o mfp2 timer1 event counter input/toggle output. uart1_n cts i mfp3 clear to send input pin for uart1 . sd _d at 2 i/o mfp4 sd /sd h mode data line bit 2. 5 1 pb . 9 i/o mfp0 general purpose digital i/o pin. usbh_vod i mfp1 usb host bus power over voltage detector . tm1_ext i mfp2 timer1 external capture input.
n uc505 june 3 0 , 2016 page 59 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description uart1_n rts o mfp3 request to send output pin for uart 1. sd _d at 3 i/o mfp4 sd /sd h mode data line bit 3. 5 2 v dd a mfp0 power supply for i / o ports , dc 3.3v. 5 3 av ddhp a mfp0 p ower supply for analog codec headphone, dc 3.3v. 5 4 lhpout a mfp0 headphone left channel output pin . 55 vcmbf a mfp0 vcm buffer output pin for headphone driver capless application . 56 rhpout a mfp0 headphone right channel output pin . 57 av sshp a mfp0 g round for analog codec headphone. 58 vmid a mfp0 headphone reference power. 59 av ddcodec a mfp0 power supply for analog codec , dc 3.3v. 60 mic 0 _ p a mfp0 microphone 0 positive input. 61 mic 0 _ n a mfp0 microphone 0 negative input. 62 mic_bias a mfp0 codec left line - in channel or microphone bias. 63 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 64 pd . 2 i/o mfp0 general purpose digital i/o pin. mic 1 _ p a mfp 1 microphone 1 positive input. 65 pd . 3 i/o mfp0 general purpose digital i/o pin. mic 1 _ n a mfp 1 microphone 1 negative input. 66 pd . 4 i/o mfp0 general purpose digital i/o pin. rlinein a mfp 1 codec right line - in channel . 67 a v dd adc a mfp0 p ower supply for analog sar - adc, dc 3.3v. 68 a v ss adc a mfp0 g round pin for analog sar - adc. 69 pa . 0 i/o mfp0 general purpose digital i/o pin. adc _ch 0 a mfp1 adc channel 0 analog input . 70 pa . 1 i/o mfp0 general purpose digital i/o pin. adc _ch 1 a mfp1 adc channel 1 analog input .
n uc505 june 3 0 , 2016 page 60 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description 71 pa . 2 i/o mfp0 general purpose digital i/o pin. adc _ch 2 a mfp1 adc channel 2 analog input . i2s_mclk o mfp2 i 2 s master clock output pin. 72 pa . 3 i/o mfp0 general purpose digital i/o pin. adc _ch 3 a mfp1 adc channel 3 analog input . i2s_di i mfp2 i 2 s data input. 73 pa . 4 i/o mfp0 general purpose digital i/o pin. adc _ch 4 a mfp1 adc channel 4 analog input . i2s_do o mfp2 i 2 s data output. 74 pa . 5 i/o mfp0 general purpose digital i/o pin. adc _ch 5 a mfp1 adc channel 5 analog input . 75 pa . 6 i/o mfp0 general purpose digital i/o pin. adc _ch 6 a mfp1 adc channel 6 analog input . 76 pa . 7 i/o mfp0 general purpose digital i/o pin. adc _ch 7 a mfp1 adc channel 7 analog input . 77 v dd12 a mfp0 power supply for i / o ports , dc 1.2 v 78 pb . 10 i/o mfp0 general purpose digital i/o pin. spi 1 _ss o mfp1 spi 1 slave select pin. i2c1_ scl o mfp2 i2c 1 clock pin. uart2_ txd o mfp3 data transmitter output pin for uart2. pwm _ch0 i/ o mfp4 pwm channel0 output/capture input. 79 pb . 11 i/o mfp0 general purpose digital i/o pin. spi 1 _clk o mfp1 spi 1 serial clock pin. i2c1_ sda i/o mfp2 i2c 1 data input/output pin. urat2_ rxd i mfp3 d ata receiver input pin for uart2 . pwm _ch1 i/ o mfp4 pwm channel1 output/capture input.
n uc505 june 3 0 , 2016 page 61 of 130 rev 1.0 6 nuc505 series datasheet pin no . pin name type mfp description 80 pb . 12 i/o mfp0 general purpose digital i/o pin. spi 1 _ mosi o mfp1 spi 1 mosi (master out, slave in) pin. u sbh 1 _d + i/o mfp2 usb host - lite 1 differential signal d+ . uart2_n cts i mfp3 clear to send input pin for uart2 . pwm _ch2 i/ o mfp4 pwm channel2 output/capture input. 81 v dd a mfp0 power supply for i / o ports , dc 3.3v. 82 pc . 11 i/o mfp0 general purpose digital i/o pin. i2s_lrclk i/ o mfp1 i 2 s left right channel clock. tm3_cnt_out i/o mfp2 timer3 event counter input/toggle output. pwm _ch2 i/ o mfp3 pwm channel2 output/capture input. 83 pc . 12 i/o mfp0 general purpose digital i/o pin. i2s_bclk i/ o mfp1 i 2 s bit clock pin. tm3_ext i mfp2 timer3 external capture input. pwm _ch3 i/o mfp3 pwm channel3 output/capture input. 84 pc . 13 i/o mfp0 general purpose digital i/o pin. u sbh 2 _d + i/o mfp1 usb host - lite 2 differential signal d+. 85 pc . 14 i/o mfp0 general purpose digital i/o pin. u sbh 2 _d - i/o mfp1 usb host - lite 2 differential signal d - . 86 v dd a mfp0 power supply , dc 3.3v . 87 ldo_cap a mfp0 ldo output pin. 88 v ss a mfp0 ground. note: the thermal pad (epd) on the bottom of qfn package should be connected to gnd.
n uc505 june 3 0 , 2016 page 62 of 130 rev 1.0 6 nuc505 series datasheet 4.3.8 summary gpio multi - function pin description mpf0 mpf1 mpf2 mpf3 mpf4 other driving pa . 0 adc _ch 0 2~16ma pa . 1 adc _ch 1 2~16ma pa . 2 adc _ch 2 2~16ma pa . 3 adc _ch 3 2~16ma pa . 4 adc _ch 4 2~16ma pa . 5 adc _ch 5 2~16ma pa . 6 adc _ch 6 2~16ma pa . 7 adc _ch 7 2~16ma pa . 8 spim_ss i2s_lrclk uart1_ txd 8ma pa . 9 spim_clk i2s_bclk uart1_ rxd syscfg[0] 8ma pa . 10 spim_ mosi i2c1_ scl sd _clk syscfg[1] 8ma pa . 11 spim_ miso i2c1_ sda sd _cmd 8ma pa . 12 spim_d2 tm0_cnt_out 8ma pa . 13 spim_d3 tm 0 _ext sd _ n cd 8ma pa . 14 i2c0_ scl sd _d at 0 4ma pa . 15 i2c0_ sda sd _d at 1 4ma pb . 0 i2c0_ scl uart0_ txd sd _d at 2 4ma pb . 1 i2c0_ sda uart0_ rxd sd _d at 3 4ma pb . 2 spi0_ss sd _cmd 4ma pb . 3 spi0_clk sd _clk syscfg[2] 4ma pb . 4 spi0_ mosi syscfg[3] 4ma pb . 5 spi0_ miso sd _ n cd 4ma pb . 6 uart1_ txd sd _d at 0 4ma pb . 7 uart1_ rxd sd _d at 1 4ma pb . 8 usb h _pwen tm1_cnt_out uart1_n ct s sd _d at 2 4ma pb . 9 usbh_ovd tm1_ext uart1_n rt s sd _d at 3 4ma pb . 10 spi1_ss i2c1_ scl uart2_ txd pwm _ ch0 4ma pb . 11 spi1_clk i2c1_ sda uart2_ rxd pwm _ch1 4ma pb . 12 spi1_ mosi usbh 1 _d + uart2_n cts pwm _ ch2 8ma pb . 13 spi1_ miso usbh 1 _d - uart2_n rst pwm _ ch3 8ma pb . 14 u sbh 1 _d + i2c1_ scl 8ma pb . 15 u sbh 1 _d - i2c1_ sda 8ma
n uc505 june 3 0 , 2016 page 63 of 130 rev 1.0 6 nuc505 series datasheet pc . 0 sd _cmd 8ma pc . 1 sd _clk 8ma pc . 2 sd _ n cd 8ma pc . 3 8ma pc . 4 sd _d at 0 8ma pc . 5 sd _d at 1 8ma pc . 6 sd _d at 2 8ma pc . 7 sd _d at 3 8ma pc . 8 i2s_mclk 4ma pc . 9 i2s_di tm2_cnt_out pwm _ch0 4ma pc . 10 i2s_do tm2_ext pwm _ch1 4ma pc . 11 i2s_lrclk tm3_cnt_out pwm _ch2 4ma pc . 12 i2s_bclk tm3_ext pwm _ch3 4ma pc . 13 u sbh 2 _d + 8ma pc . 14 u sbh 2 _d - 8ma pd . 0 i2c0_ scl ice_clk 4ma pd . 1 i2c0_ sda ice_dat 4ma pd . 2 mic 1 _ p 2~16ma pd . 3 mic 1 _ n 2~16ma pd . 4 rlinein 2~16ma
n uc505 june 3 0 , 2016 page 64 of 130 rev 1.0 6 nuc505 series datasheet 4.3.9 gpio multi - function pin summary mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[ 2 :0]=0x0. pa.9 mfp5 means sys_gpa_mfph[ 6 :4]=0x5. group pin name gpio mfp * type description adc adc _ch0 p a .0 mfp1 a adc0 analog input. adc_ch1 p a .1 mfp1 a adc1 analog input. adc_ch2 p a .2 mfp1 a adc2 analog input. adc_ch3 p a .3 mfp1 a adc3 analog input. adc_ch4 p a . 4 mfp1 a adc4 analog input. adc_ch5 p a . 5 mfp1 a adc5 analog input. adc_ch6 p a . 6 mfp1 a adc6 analog input. adc_ch7 p a . 7 mfp1 a adc7 analog input. codec mic 1 _p pd.2 mfp1 a audio mic 1 analog positive input pin mic 1 _n pd.3 mfp1 a audio mic 1 analog negative input pin rlinein pd.4 mfp1 a audio right line - in analog pin. i2c0 i2c0_scl pa.14 mfp2 i/o i2c0 clock pin. i2c0_scl pb.0 mfp2 i/o i2c0 clock pin. i2c0_scl pd.0 mfp2 i/o i2c0 clock pin. i2c0_sda pa.15 mfp2 i/o i2c0 data input/output pin. i2c0_sda pb.1 mfp2 i/o i2c0 data input/output pin. i2c0_sda pd.1 mfp2 i/o i2c0 data input/output pin. i2c1 i2c 1 _scl pa.10 mfp2 i/o i2c 1 clock pin. i2c 1 _scl pb.10 mfp2 i/o i2c 1 clock pin. i2c 1 _scl pb.14 mfp2 i/o i2c 1 clock pin. i2c 1 _sda pa.11 mfp2 i/o i2c 1 data input/output pin. i2c 1 _sda pb.11 mfp2 i/o i2c 1 data input/output pin. i2c 1 _sda pb.15 mfp2 i/o i2c 1 data input/output pin. i 2 s i2s_mclk pa.2 mfp2 o i 2 s master clock output pin. i2s_mclk pc.8 mfp1 o i 2 s master clock output pin. i2s_bclk pa.9 mfp2 i/o i 2 s bit clock pin. i2s_bclk pc.12 mfp1 i/o i 2 s bit clock pin. i2s_lrclk pa.8 mfp2 i/o i 2 s left right channel pin. i2s_lrclk pc.11 mfp1 i/o i 2 s left right channel pin.
n uc505 june 3 0 , 2016 page 65 of 130 rev 1.0 6 nuc505 series datasheet group pin name gpio mfp * type description i2s_do pa.4 mfp2 o i 2 s data output. i2s_do pc.10 mfp1 o i 2 s data output. i2s_di pa.3 mfp2 i i 2 s data input. i2s_di pc.9 mfp1 i i 2 s data input. ice ice_clk p d . 0 mfp0 i serial wired debugger clock pin ice_dat p d.1 mfp0 i/o serial wired debugger data pin pwm pwm_ch0 pb.10 mfp4 i/o pwm output/capture input. pwm_ch0 pc.9 mfp3 i/o pwm output/capture input. pwm_ch1 pb.11 mfp4 i/o pwm output/capture input. pwm_ch1 pc.10 mfp3 i/o pwm output/capture input. pwm_ch2 pb.12 mfp4 i/o pwm output/capture input. pwm_ch2 pc.11 mfp3 i/o pwm output/capture input. pwm_ch3 pb.13 mfp4 i/o pwm output/capture input. pwm_ch3 pc.12 mfp3 i/o pwm output/capture input. spim spim_ss pa.8 mfp1 o spim slave select pin. spim_clk pa.9 mfp1 o spim serial clock pin. spim_mosi pa.10 mfp1 i/o spim mosi (master out, slave in) pin. spim_miso pa.11 mfp1 i/o spi m miso (master in, slave out) pin. spim_d2 pa.12 mfp1 i/o spim data - 2 bit in quad mode. spim_d3 pa.13 mfp1 i/o spim data - 3 bit in quad mode. spi0 spi0_ss pb.2 mfp1 o spi0 slave select pin. spi0_clk pb.3 mfp1 o spi0 serial clock pin. spi0_mosi pb.4 mfp1 i/o spi0 mosi (master out, slave in) pin. spi0_miso pb.5 mfp1 i/o spi0 miso (master in, slave out) pin. spi1 spi1_ss pb.10 mfp1 o spi1 slave select pin. spi1_clk pb.11 mfp1 o spi1 serial clock pin. spi1_mosi pb.12 mfp1 i/o spi1 mosi (master out, slave in) pin. spi 1 _miso pb.13 mfp1 i/o spi 1 miso (master in, slave out) pin. timer tm0_cnt_out pa.12 mfp2 i/o timer0 event counter input / toggle output . tm0_ext pa.13 mfp2 i timer0 external counter input tm1_cnt_out pb.8 mfp2 i/o timer 1 event counter input / toggle output . tm1_ext pb.9 mfp2 i timer 1 external counter input tm2_cnt_out pc.9 mfp2 i/o timer 2 event counter input / toggle output .
n uc505 june 3 0 , 2016 page 66 of 130 rev 1.0 6 nuc505 series datasheet group pin name gpio mfp * type description tm2_ext pc.10 mfp2 i timer 2 external counter input tm3_cnt_out pc.11 mfp2 i/o timer 3 event counter input / toggle output . tm3_ext pc.12 mfp2 i timer 3 external counter input uart0 uart0_rxd p b . 1 mfp3 i data receiver input pin for uart0. uart0_txd p b . 0 mfp3 o data transmitter output pin for uart0. uart1 uart1_rxd pa.9 mfp3 i data receiver input pin for uart1. uart1_rxd pb.7 mfp3 i data receiver input pin for uart1. uart1_txd pa.8 mfp3 o data transmitter output pin for uart1. uart1_txd pb.6 mfp3 o data transmitter output pin for uart1. uart1_ncts pb.8 mfp3 i clear to send input pin for uart1. uart1_nrts pb.9 mfp3 o request to send output pin for uart1. uart2 uart2_rxd pb.11 mfp3 i data receiver input pin for uart2. uart2_txd pb.10 mfp3 o data transmitter output pin for uart2. uart2_ncts pb.12 mfp3 i clear to send input pin for uart2. uart2_nrts pb.13 mfp3 o request to send output pin for uart2. usb host lite usb h _pwen pb.8 mfp1 o usb host to control an external overcurrent source . usbh_vod pb.9 mfp1 i usb host lite over voltage detector usbh2 _d+ pc.13 mfp1 a usb host lite 2 differential signal d+. usbh2 _d - pc.14 mfp1 a usb host lite 2 differential signal d - . usbh1_d+ pb.12 mfp2 a usb host lite 1 differential signal d+. usbh1_d+ pb.14 mfp1 a usb ho st lite 1 differential signal d+ . usbh1_d - pb.13 mfp2 a usb ho st lite 1 differential signal d - . usbh1_d - pb.15 mfp1 a usb host lite 1 differential signal d - . sd h sd_clk pa.10 mfp4 o sd/ sdh mode - clock sd_clk pb.3 mfp4 o sd/ sdh mode C clock sd_clk pc.1 mfp1 o sd/ sdh mode C clock sd_cmd pa.11 mfp4 o sd/ sdh mode C command/response sd_cmd pb.2 mfp4 o sd/sd h mode C command/response sd_cmd pc.0 mfp1 o sd/sd h mode C command/response sd_ncd pa.13 mfp4 i sd/sd h mode C card detect. sd_ncd pb.5 mfp4 i sd/sd h mode C card detect. sd_ncd pc.2 mfp1 i sd/sd h mode C card detect. sd_dat0 pa.14 mfp4 i/o sd/sd h mode data line bit 0.
n uc505 june 3 0 , 2016 page 67 of 130 rev 1.0 6 nuc505 series datasheet group pin name gpio mfp * type description sd_dat0 pb.6 mfp4 i/o sd/sd h mode data line bit 0. sd_dat0 pc.4 mfp1 i/o sd/sd h mode data line bit 0. sd_dat1 pa.15 mfp4 i/o sd/sd h mode data line bit 1. sd_dat1 pb.7 mfp4 i/o sd/sd h mode data line bit 1. sd_dat1 pc.5 mfp1 i/o sd/sd h mode data line bit 1. sd_dat2 pb.0 mfp4 i/o sd/sd h mode data line bit 2. sd_dat2 pb.8 mfp4 i/o sd/sd h mode data line bit 2. sd_dat2 pc.6 mfp1 i/o sd/sd h mode data line bit 2. sd_dat3 pb.1 mfp4 i/o sd/sd h mode data line bit 3. sd_dat3 pb.9 mfp4 i/o sd/sd h mode data line bit 3. sd_dat3 pc.7 mfp1 i/o sd/sd h mode data line bit 3. table 4.3 - 1 nuc505 gpio multi - function table
n uc505 june 3 0 , 2016 page 68 of 130 rev 1.0 6 nuc505 series datasheet 5 block diagram numicro ? nuc 505 series block diagram 5.1 figure 5.1 - 1 numicro ? nuc505 block diagram c l o c k c o n t r o l s y s t e m p l l a u d i o p l l h s e x t . c r y s t a l o s c . 1 2 m h z l i r c / l s e x t . c r y s t a l o s c . 3 2 . 7 6 8 k h z c o n n e c t i v i t y s d h o s t u s b 2 . 0 f u l l s p e e d h o s t u s b 2 . 0 h i g h s p e e d d e v i c e s p i m c o n n e c t i v i t y i 2 c x 2 s p i x 2 u a r t x 3 g e n e r a l p u r p o s e i / o s r a m 1 2 8 k b m e m o r y p o w e r c o n t r o l l d o 1 . 2 v p o r , l v r , l v d a d c / a u d i o / o t p 1 2 - b i t a d c w i t h 8 - c h 2 4 - b i t a u d i o c o d e c i 2 s m u l t i - e n t r y o t p a r m c o r t e x ? _ m 4 ( d s p & f p u ) 1 0 0 m h z t i m e r / p w m 3 2 - b i t t i m e r 4 - c h r t c ( r t c _ v d d 3 3 ) w a t c h d o g t i m e r s p w m 4 - c h a h b b u s a p b b u s
n uc505 june 3 0 , 2016 page 69 of 130 rev 1.0 6 nuc505 series datasheet 6 functional description arm ? cortex ? - m4 core 6.1 the cortex ? - m 4 processor , a configurable, multistage, 32 - bit risc processor , has three amba ahb - lite interface s for best parallel performance and includes a nvic component. the processor has optional hardware debug function ality , which can execute thumb code , and is compatible with other cortex ? - m profile processor s . the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in han dler mode. thread mode is entered on reset, and can be entered as a result of an exception return. the cortex ? - m4f is a processor with the same capability as the cortex ? - m4 processor and includes floating point arithmetic functionality. the nuc505 is embed ded with cortex ? - m4f processor. throughout this document the name cortex ? - m4 refers to both cortex ? - m4 and cortex ? - m4f processors. the following figure shows the functional controller of the processor. figure 6.1 - 1 cortex ? - m4 block diagram cortex ? - m4 processor features : ? a low gate count processor core, with low latency interrupt processing that has : a subset of the thumb instruction set, defined in the armv7 - m architecture reference m anual .
n uc505 june 3 0 , 2016 page 70 of 130 rev 1.0 6 nuc505 series datasheet banked stack pointer (sp) . hardware integer divide instructions, sdiv and udiv. handler and thread modes. thumb and debug states. support for interruptible - continued instructions ldm, stm, push, and pop for low interrupt latency . automatic processor state saving and restoration for low latency interrupt service routine (isr) entry and exit. support for armv6 big - endian byte - invariant or little - endian accesses. support for armv6 unaligned accesses. ? floating point unit (fpu) in the cortex ? - m4f processor providing: 32 - bit instructions for single - precision (c float) data - processing operations. combined multiply and accumulate instructions for increased precision (fused mac). hardware support for conversion, addition, subtraction, multi plication with optional accumulate, division, and square - root. hardware support for denormals and all ieee rounding modes. 32 dedicated 32 - bit single precision registers, also addressable as 16 double - word registers. decoupled three - stage pipeline . ? nested vectored interrupt controller (nvic) closely integrated with the processor core to achieve low latency interrupt processing. features include: external interrupts. c onfigurable from 1 to 240; the nuc505 has been configured with 32 interrupts. bits of prio rity, configurable from bit 3 to bit 7. dynamic reprioritization of interrupts. supports priority grouping which enables selection of preempting interrupt levels and non - preempting interrupt levels. supports tril - chaining and late arrival of interrupts, wh ich enables back - to - back interrupt processing without the overhead of state saving and restoration between interrupts. processor state automatically saved on interrupt entry, and restored on interrupt exit with on instruction overhead. supports wake - up in terrupt controller (wic) with power - down mode . ? memory protection unit (mpu). an optional mpu for memory protection, including: eight memory regions. sub region disable (srd), enabling efficient use of memory regions. the ability to enable a background region that implements the default memory map attributes. ? low - cost debug solution that features:
n uc505 june 3 0 , 2016 page 71 of 130 rev 1.0 6 nuc505 series datasheet debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, a nd access to debug control registers even while sysresetn is asserted. serial wire debug port (sw - dp) or serial wire jtag debug port (swj - dp) debug access. but nuc505 only supports sw - dp. optional flash patch and breakpoint (fpb) unit for implementing breakpoints and code patches. optional data watchpoint and trace (dwt) unit for implementing watchpoints, data tracing, and system profiling. ? bus interfaces: three advanced high - performance bus - lite (ahb - lite) interfaces: icode, dcode, and system bus inte rfaces. private peripheral bus (ppb) based on advanced peripheral bus (apb) interface. bit - band support that includes atomic bit - band write and read operations. memory access alignment. write buffer for buffering of write data. exclusive access transfers f or multiprocessor systems.
n uc505 june 3 0 , 2016 page 72 of 130 rev 1.0 6 nuc505 series datasheet system manager 6.2 6.2.1 overview the following functions are included in system manager section ? system reset ? system memory map ? bus arbitration algorithm ? global control registers ? system timer (systick) ? nested vectored interrupt control (nvic) ? system control register map and description 6.2.2 system reset ? hardware reset power - on reset (por) low level on the nreset pin (nrst) watchdog time - out reset (wdt) low voltage reset (lvr) ? software reset sysresetreq (aircr[2]) cpu reset ( sys_iprst0 [0]) chi prst ( sys_iprst0 [1]) note1: sysresetreq ( aircr[2] ) reset the whole chip including all peripherals , but does not reset spim function , vector map module parameter setting, and pa . 8~pa . 15 multi - function setting . note2: cpu rest (sys_iprst0[0]) only resets the cpu function. note3: chiprst (sys_iprst0[1]) reset the whole chip including all peripherals.
n uc505 june 3 0 , 2016 page 73 of 130 rev 1.0 6 nuc505 series datasheet 6.2.3 system power - o n setting the power - on setting is used to configure the chip to enter the specified state when the chip is powered up or reset. since each pin of power - on setting has an internal pulled - up resistor during reset period , i f the application needs to set the configuration to 0 , the proper pull - down must be added for the corresponding configuration pins. pb . 4 pb . 3 pa . 1 0 pa . 9 description register mapping 1 1 1 1 boot from i n ternal mcp spi flash sys_bootset [3:0] 1 1 1 0 boot from usb sys_bootset [3:0] 1 1 0 1 boot from external spi flash sys_bootset [3:0] 1 0 1 1 boot from icp mode sys_bootset [3:0] 0 1 1 1 sw d/ice mode with internal spi flash sys_bootset [3:0] 0 1 1 0 sw d/ice mode with external spi flash sys_bootset [3:0] table 6.2 - 1 system power - o n setting guide 6.2.4 system power distribution in this chip, power distribution is divided into five segments : ? audio codec power from av dd codec, av ddhp , and av sshp provides the power for audio codec op eration. ? analog - to - digital converter (adc) power from av dd adc and av ssadc provides the power for adc op eration. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1. 2 v power for digital operation and i/o pins. ? usb transceiver power from usb_ vbus offers the power for operating the usb transceiver. ? rtc power from v bat provides the power for rtc and 80 bytes backup registers. the outputs of internal voltage regulators, ldo and v dd , require an external capacitor which should be located close to the corresponding pin. analog power (av dd codec and av ddadc ) should be the same voltage level of the digital p ower (v dd ). the following figure shows the power distribution of the numicro ? nuc505 .
n uc505 june 3 0 , 2016 page 74 of 130 rev 1.0 6 nuc505 series datasheet figure 6.2 - 1 numicro ? nuc505 power distribution diagram 6.2.5 system memory mapping the nuc505 provides a 4g - byte address space for programmers. the memory locations assigned to each on - chip modules are shown in table 6.2 - 2 . the detailed registers and memory addressing or programming will be described in the following sections for individual on - chip modules. the nuc505 only supports little - endian data format. address space token modules memory space 0x1fff_0000 C 0x1fff_7fff ibr_ba internal boot rom (ibr) memory space u s b t r a n s c e i v e r a v d d h p a v s s h p v d d v s s a v d d u s b u s b _ d + u s b _ d - s r a m p l l i o c e l l 3 . 3 v 1 . 2 v l d o p o r 3 3 p o r 1 2 l o w v o l t a g e d e t e c t o r l o w v o l t a g e r e s e t 2 4 - b i t a u d i o c o d e c 1 2 m h z c r y s t a l o s c i l l a t o r d i g i t a l l o g i c 1 2 - b i t a d c p o w e r o n c o n t r o l x t 1 _ o u t x t 1 _ i n g p i o 1 . 2 v 3 . 3 v 3 . 3 v l d o _ c a p 4 . 7 u f n u c 5 0 5 p o w e r d i s t r i b u t i o n a v d d c o d e c a v d d a d c a v s s a d c 3 . 3 v 3 . 3 v v b a t 3 2 . 7 6 8 k h z c r y s t a l o s c i l l a t o r r t c 3 2 b y t e s b a c k u p r e g i s t e r x 3 2 _ i n x 3 2 _ o u t 3 . 3 v
n uc505 june 3 0 , 2016 page 75 of 130 rev 1.0 6 nuc505 series datasheet 0x2000_0000 C 0x2000_7fff sram1_ba sram1 memory space (32k bytes) 0x2000_8000 C 0x2000_ffff sram2_ba sram2 memory space (32k bytes) 0x2001_0000 C 0x2001_7fff sram3_ba sram3 memory space (32k bytes) 0x2001_8000 C 0x2001_ffff sram4_ba sram4 memory space (32k bytes) 0x0000_0000 C 0x0fff_ffff flash_ba spi flash/rom memory space ahb controller s space (0x4000_0000 ~0x4000ffff) 0x4000_0000 C 0x4000_01ff gcr_ba global control registers 0x4000_0200 C 0x4000_02ff clk_ba clock control registers 0x4000_7000 C 0x4000_7fff spim_ba spim control register 0x4000_9000 C 0x4000_9fff usbd_ba usb device controller registers 0x4000_a000 C 0x4000_afff sdh_ba sdh control register 0x4000_b000 C 0x4000_bfff usbh_ba usb host controller registers apb controllers space (0x400e_0000~0x400e_ffff) 0x400e_1000 C 0x400e_1fff spi1_ba spi1 master/slave controller registers (spi1) 0x400e_2000 C 0x400e_2fff adc_ba adc controller registers 0x400e_3000 C 0x400e_3fff gpio_ba gpio controller registers 0x400e_4000 C 0x400e_4fff i2c0_ba i2c0 interface control registers 0x400e_5000 C 0x400e_5fff i2c1_ba i2c1 interface control registers 0x400e_6000 C 0x400e_6fff pwm_ba pwm controller registers 0x400e_7000 C 0x400e_7fff rtc_ba real time clock (rtc) control register 0x400e_8000 C 0x400e_8fff i2s_ba inter - ic sound (i 2 s) control register 0x400e_9000 C 0x400e_9fff spi0_ba spi0 master/slave controller registers (spi0) 0x400e_a000 C 0x400e_afff timer01_ba timer0/timer1 control registers 0x400e_b000 C 0x400e_bfff timer23_ba timer2/timer3 control registers 0x400e_c000 C 0x400e_cfff uart0_ba uart0 control registers (normal speed) 0x400e_d000 C 0x400e_dfff uart1_ba uart1 control registers (high speed) 0x400e_e000 C 0x400e_efff uart2_ba uart2 control registers (high speed) 0x400e_f000 C 0x400e_ffff wdt_ba wdt interface control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 C 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f scs_ba system control registers table 6.2 - 2 address space assignments for on - chip controllers
n uc505 june 3 0 , 2016 page 76 of 130 rev 1.0 6 nuc505 series datasheet 6.2.6 sram memory organization the nuc505 supports embedded sram with a total of 128 kbytes and the sram organization is separated to four banks: sram bank0, sram bank1, sram bank2, and sram bank3. each of these four banks has 32 kbytes address space and can be accessed simultaneously. ? supports a total of 128 kbytes sram ? supports byte / half word / word write ? supports fixed 32 kbytes sram banks for independent access ? supports remap address to 0x1ff0_0000 ? supports remap arbitrary memory block of 128 kbytes sram to 0x0000_0000 by using vector map module figure 6.2 - 2 sram block diagram figure 6.2 - 3 shows the sram organization of nuc505. there are four sram banks in nuc505 and each bank is addressed to 32 kbytes. the bank0 address space is from 0x2000_0000 to 0x2000_7fff. the bank1 addre ss space is from 0x2000_8000 to 0x2000_ffff. the bank2 address space is from 0x2001_0000 to 0x2001_7fff. the bank3 address space is from 0x2001_8000 to 0x2001_ffff. the address of each bank is remapping from 0x2000_0000 to 0x1ff0_0000. cpu can access sram bank0 through 0x2000_0000 to 0x2000_7fff or 0x1ff0_0000 to 0x1ff0_7fff, sram bank1 through 0x2000_8000 to 0x2000_ffff or 0x1ff0_8000 to 0x1ff0_ffff, sram bank2 through 0x2001_0000 to 0x2001_7fff or 0x1ff1_0000 to 0x1ff1_7fff, and sram bank3 through 0x2001_ 8000 to 0x2001_ffff or 0x1ff1_8000 to 0x1ff1_ffff. ahb bus ahb interface controller sram decoder sram bank 0 sram bank 1 sram decoder ahb interface controller ahb interface controller sram decoder sram bank 2 ahb interface controller sram decoder sram bank 3
n uc505 june 3 0 , 2016 page 77 of 130 rev 1.0 6 nuc505 series datasheet figure 6.2 - 3 sram memory o rganization figure 6.2 - 4 shows the vector map module diagram. arbitrary memory block in 128 kbytes sram can be remapped to the spi flash block and its start address is 0x0000_0000. the location and size with the memory block are controlled by the register sys_rvmpaddr[31:0] and th e register sys_rvmplen[31:24]. the sys_rvmpaddr indicate s the start address of the memory block a nd sys_rvmplen describes about the size of the memory block (the unit is 1 kbyte). 512 mb 32 k byte sram bank 0 0 x 2000 _ 0000 reserved 0 x 3 fff _ ffff 32 k byte sram bank 1 0 x 2000 _ 7 fff 0 x 2000 _ ffff 0 x 2000 _ 8000 0 x 2001 _ 0000 128 k byte device 0 x 1 ff 0 _ 0000 0 x 1 ff 0 _ 7 fff 0 x 1 ff 0 _ ffff 0 x 1 ff 0 _ 8000 128 k byte device remapping remapping 0 x 1 ff 1 _ 0000 0 x 1 ff 1 _ 7 fff 0 x 1 ff 1 _ ffff 0 x 1 ff 1 _ 8000 0 x 2001 _ 7 fff 0 x 2001 _ ffff 0 x 2001 _ 8000 0 x 2002 _ 0000 32 k byte sram bank 2 32 k byte sram bank 3 32 k byte sram bank 0 32 k byte sram bank 1 32 k byte sram bank 2 32 k byte sram bank 3 remapping remapping
n uc505 june 3 0 , 2016 page 78 of 130 rev 1.0 6 nuc505 series datasheet figure 6.2 - 4 vector map module block 6.2.7 ahb bus arbitration the internal bus of nuc505 is an ahb - compliant bus and supports to connect with the standard ahb master or slave. the nuc505 ahb arbiter provides a choice of two arbitration algor ithms for simultaneous requests. these two arbitration algorithms are the fixed - priority mode and the r ound - robin - priority (rotate) mode. the selection of modes and types is determined in the prisel field of the sys_ahbctl control register . fixed priority mode 6.2.7.1 fixed priority mode is selected if prisel = 0. the order of priorities on the ahb mastership among the on - chip master modules are listed in table 6.2 - 3 . priority sequence ( prisel = 0) ahb bus priority 1 (lowest) cortex - m4 i 2 cortex - m4 d 3 cortex - m4 system 4 spi m 5 usbd spi flash 0 x 2000 _ ab 00 0 x 2000 _ b 2 ff 2 kbytes 2 kbytes 0 x 2000 _ 0000 0 x 2001 _ ffff 0 x 0000 _ 0000 0 x 0000 _ 07 ff 0 x 0000 _ 0800 0 x 001 f _ ffff 2 mb 128 kb sram vector mapping sys _ rvmpaddr [ 31 : 0 ] = 0 x 2000 _ ab 00 sys _ rvmplen [ 31 : 24 ] = 0 x 02 example :
n uc505 june 3 0 , 2016 page 79 of 130 rev 1.0 6 nuc505 series datasheet 6 u sbh 6 sd h 8 (highest) i 2 s table 6.2 - 3 ahb bus priority order in fixed priority mode if two or more master modules request to access ahb bus at the same time, the higher priority request will get the permission to access ahb bus. priority sequence ( prisel = 0) ahb bus priority 1 (lowest) cortex - m4 i 2 cortex - m4 d 3 cortex - m4 system 4 spi m 5 usbd 6 u sbh 6 sd h 8 (highest) i 2 s table 6.2 - 3 ahb bus priority order in fixed priority mode the spi flash controller normally has the lowest priority (except cpu interface) under the fixed priority mode. the nuc50 5 provides a mechanism to raise the priority of cpu request to the highest. if the cpuhpri bit (bit - 4 of sys_ahbctl c ontrol r egister ) is set to 1, the prists bit (bit - 5 of sys_ahbctl c ontrol r egister ) will be automatically set to 1 while an unmasked external irq occurs. under this circumstance, the arm core will become the highest priority to access ahb bus. the programmer can recover the original priority order by directly writing 1 to clear the prists bit. for example, this can be done that at the end of an interrupt service routine. note that prists only can be automatically set to 1 by an external interrupt when cpuhpri = 1. it wi ll not take effect for a programmer to directly write 1 to prists to raise arm cores ahb priority. round robin priority mode 6.2.7.2 round - robin priority mode is selected if p risel = 1. the ahb bus arbiter uses a round robin arbitration scheme for every master module to gain the bus ownership in turn. that is the requestor having the highest priority becomes the lowest - priority requestor after it has been granted access . rotate rul e example 6.2.7.3 in the default sequence of ahb master bus, the priority is i 2 s > sdh > usbh > usbd > spi m > m4(s) > m4(d) > m4(i) .
n uc505 june 3 0 , 2016 page 80 of 130 rev 1.0 6 nuc505 series datasheet 6.2.8 system timer (systick) the cortex ? - m4 includes an integrated system timer, systick, which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current v alue register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle, and then decrement on subsequent clocks. when the counter transitions to zero, the countflag status bit is set. the co untflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, plea se refer to the arm ? cortex ? - m4 technical reference manual and arm ? v6 - m architecture reference manual.
n uc505 june 3 0 , 2016 page 81 of 130 rev 1.0 6 nuc505 series datasheet 6.2.9 nested vectored interrupt control (nvic) the nvic and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. the nvic maintains knowledge of the stacked, or nested, interrupts to enable tail - chaining of int errupts. users can only fully access the nvic from privileged mode, but this may cause interrupts to enter a pending state in user mode if enabl ing the configuration and control register. any other user mode access causes a bus fault. users can access all nvic registers using byte, halfword, and word accesses unless otherwise stated. nvic registers are located within the scs (system control space). all nvic registers and system debug registers are little - endian regardless of the endianness state of the proc essor. ? an implementation - defined number of interrupts, in the range 1 - 240 interrupts. ? a programmable priority level of 0 - 16 for each interrupts. a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ? level and pulse d etection of interrupt signals. ? dynamic reprioritization of interrupts. ? grouping of priority values into group priority and subpriority fields. ? interrupt tail - chaining. ? an external non maskable interrupt (nmi) ? wic, providing power - down mode support. the pro cessor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. this provides low latency exception handling. exception model and system interrupt map 6.2.9.1 the following table lists the exception model supported by nuc505 series. software can set 16 levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0x00 and the lowest priority i s denoted as 0xf0 (the 4 - lsb always 0). the default priority of all the user - configurable interrupts is 0x00. note that priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. when a ny interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. on system reset, the vector table is fixed at address 0x00000000. privileged software can write to the vtor to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3fffff80, the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception h andlers. the vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section.
n uc505 june 3 0 , 2016 page 82 of 130 rev 1.0 6 nuc505 series datasheet table 6.2 - 4 exception model vector number interrupt number interrupt name interrupt description (bit in interrupt registers) 0 ~ 15 - - system exceptions 16 0 pwr_int power on interrupt 1 7 1 wdt_int watch dog timer interrupt 1 8 2 reserved reserved 19 3 i2s_int i 2 s interrupt 20 4 eint 0_int external gpio group 0 interrupt 21 5 eint 1_int external gpio group 1 interrupt 2 2 6 eint 2_int external gpio group 2 interrupt 2 3 7 eint 3_int external gpio group 3 interrupt 2 4 8 spim_int spi m interrupt 2 5 9 usbd_int usb device 20 interrupt 2 6 10 tm0_int timer0 interrupt 2 7 11 tm1_int timer1 interrupt 2 8 12 tm2_int timer2 interrupt exception type vector number vector address priority reset 1 0x00000004 - 3 nmi 2 0x00000008 - 2 hard fault 3 0x0000000c - 1 memory manager fault 4 0x00000010 configurable bus fault 5 0x00000014 configurable usage fault 6 0x00000018 configurable reserved 7 ~ 10 reserved svcall 11 0x0000002c configurable debug monitor 12 0x00000030 configurable reserved 13 reserved pendsv 14 0x00000038 configurable systick 15 0x0000003c configurable interrupt (irq0 ~ irq 31 ) 16 ~ 47 0x00000000 + (vector number)*4 configurable
n uc505 june 3 0 , 2016 page 83 of 130 rev 1.0 6 nuc505 series datasheet 2 9 13 tm3_int timer3 interrupt 30 14 sdh_int sdh interrupt 31 15 pwm0_int pwm0 interrupt 3 2 16 pwm1_int pwm1 interrupt 3 3 17 pwm2_int pwm2 interrupt 3 4 18 pwm3_int pwm3 interrupt 3 5 19 rtc_int real time clock interrupt 3 6 20 spi0_int spi0 interrupt 3 7 21 i2c1_int i2c1 interrupt 3 8 22 i2c0_int i2c0 interrupt 3 9 23 uart0_int uart0 interrupt 40 24 uart1_int uart1 interrupt 41 25 adc_int adc interrupt 4 2 26 wwdt_int window watch dog timer interrupt 4 3 27 usbh_int usb host 1.1 interrupt 4 4 28 uart2_int uart2 interrupt 4 5 29 lvd_int low voltage detection interrupt 4 6 30 spi1_int spi1 interrupt 4 7 31 reserved reserved table 6.2 - 5 interrupt number table operation description 6.2.9.2 nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to bec ome pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt . nvic interrupts can be pended/un - pended using a complementary pair of registers to those used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - c lear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts, and each interrupt uses msb 4 bits of the 8 - bit field). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
n uc505 june 3 0 , 2016 page 84 of 130 rev 1.0 6 nuc505 series datasheet clock controller 6.3 6.3.1 o verview the clock controller generates clocks for the whole chip. the clocks include ahb, apb and engine clocks for all of devices like usb device, usb host, uart and so on. there are two pll clocks, pll and apll, derived from external hxt clock input. the pll clock allows the processor to operate at a high internal clock frequency. also, t he apll is used to generate more accuracy frequency for audio codec . they also implement the power control function, include the indivi dually clock on or off control register, clock source selector and divider. these functions minimize the extra power consumption and the chip run s on the just right condition. in p ower - down mode , the controller turn s off the crystal oscillator to minimize the chip power consumption.
n uc505 june 3 0 , 2016 page 85 of 130 rev 1.0 6 nuc505 series datasheet 6.3.2 clock diagram figure 6.3 - 1 clock g enerator g lobal v iew d iagram 1 2 m h z p l l _ f o u t s r a m 0 1 r t c c p u s r a m 2 3 e x t e r n a l 3 2 . 7 6 8 k h z c p u c l k h c l k 1 2 m h z s p i m a p l l _ f o u t 1 2 m h z i n t e r n a l 3 2 . 7 6 8 k h z 1 0 e x t e r n a l 3 2 . 7 6 8 k h z p l l _ f o u t 1 0 1 2 m h z 1 / ( s y s c l k _ n + 1 ) p c l k 1 / ( p c l k d i v _ n + 1 ) i n t e r n a l 3 2 . 7 6 8 k h z i 2 c 0 i 2 c 1 r t c _ c l k s r c [ 0 ] r t c _ 3 2 k r t c _ 3 2 k 1 0 1 2 m h z c l k d i v 4 [ 2 4 ] c l k d i v 0 [ 7 ] r t c _ 3 2 k 1 0 1 2 m h z c l k d i v 4 [ 2 5 ] t m r 1 r t c _ 3 2 k 1 0 1 2 m h z c l k d i v 4 [ 2 6 ] t m r 2 r t c _ 3 2 k 1 0 1 2 m h z c l k d i v 5 [ 2 4 ] t m r 3 r t c _ 3 2 k 1 0 1 2 m h z c l k d i v 5 [ 2 5 ] w d t p l l _ f o u t 1 0 1 2 m h z c l k d i v 5 [ 2 6 ] p w m p l l _ f o u t 1 0 1 2 m h z c l k d i v 3 [ 2 0 ] u a r t 2 p l l _ f o u t 1 0 1 2 m h z c l k d i v 3 [ 1 2 ] u a r t 1 p l l _ f o u t 1 0 1 2 m h z c l k d i v 3 [ 4 ] u a r t 0 r e s e r v e d 1 2 m h z a p l l _ f o u t p l l _ f o u t c l k d i v 2 [ 2 5 : 2 4 ] 1 1 1 0 0 1 0 0 i 2 s 1 / ( t m r 2 d i v + 1 ) 1 / ( t m r 1 d i v + 1 ) t m r 0 1 / ( t m r 0 d i v + 1 ) 1 / ( p w m d i v + 1 ) 1 / ( w d g c l k _ n + 1 ) 1 / ( t m r 3 d i v + 1 ) 1 / ( u a r t 2 d i v + 1 ) 1 / ( u a r t 1 d i v + 1 ) 1 / ( u a r t 0 d i v + 1 ) 1 / ( i 2 s d i v + 1 ) p l l _ f o u t 1 0 1 2 m h z c l k d i v 2 [ 2 9 ] s p i 1 1 / ( s p i 1 _ c l k d i v + 1 ) p l l _ f o u t 1 0 1 2 m h z c l k d i v 2 [ 2 8 ] s p i 0 1 / ( s p i 0 _ c l k d i v + 1 ) p l l _ f o u t 1 0 1 2 m h z c l k d i v 1 [ 2 8 ] a d c 1 / ( a d c d i v + 1 ) 1 0 s y s t i c k c l k d i v 1 [ 3 0 ] c p u c l k 1 / ( s t i c k d i v + 1 ) 1 2 m h z p l l _ f o u t 1 0 1 2 m h z s d h c 1 / ( s d h d i v + 1 ) s y s t _ c s r [ 2 ] p l l _ f o u t 1 0 1 2 m h z u s b d 1 / ( u s b d d i v + 1 ) p l l _ f o u t 1 0 1 2 m h z u s b h 1 / ( u s b h d i v + 1 ) c l k d i v 0 [ 3 1 ] c l k d i v 0 [ 2 3 ]
n uc505 june 3 0 , 2016 page 86 of 130 rev 1.0 6 nuc505 series datasheet 6.3.3 clock generator the clock generator consists of 4 clock sources, which are listed below: ? real - time clock (rtc_clk) source can be selected from external 32.768 k hz external low speed crystal oscillator ( l xt) or 32.768 k hz internal low speed rc oscillator ( l irc) ? 12 mhz external high speed crystal oscillator (hxt) ? programmable system pll output clock frequency ( pll _ fout ) ? programmable audio pll output clock frequency (a pll _ fout ) figure 6.3 - 2 clock g enerator b lock d iagram the external crystal oscillator and two capacitors are connected to the pad x t1_in / x32_in and pad x t1_out / x32_out . the capacitance value of the t wo capacitor s may be changed for differential crystal oscillator from different vender . the load capacitance values and resistance value s must be adjusted according to the selected oscillator. the recommended load capacitance values and r esistance values as crystal oscillator c apacitance v alues r esistance v alues x t 1 _ o u t e x t e r n a l 1 2 m h z c r y s t a l ( h x t ) h x t e n ( c l k _ p w r c t l [ 0 ] ) x t 1 _ i n p l l p l l _ f o u t x 3 2 _ o u t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l ( l x t ) x 3 2 _ i n i n t e r n a l 3 2 . 7 6 8 k h z o s c i l l a t o r ( l i r c ) h x t a p l l a p l l _ f o u t 1 0 r t c _ c l k l i r c l x t r t c _ c l k s r c [ 0 ]
n uc505 june 3 0 , 2016 page 87 of 130 rev 1.0 6 nuc505 series datasheet 12 mhz 20pf 1 m ? 32.768 khz 33pf 10 m ? table 6.3 - 1 r ecommended l oad c apacitance v alues and r esistance v alues . figure 6.3 - 3 crystal o scillator c ircuit 6.3.4 power - d own m ode clock when enter ing power - down mode , system clocks, some clock sources and some peripheral clocks are disabled . some clock sources and peripherals clock are still active in power - down mode . t he clocks which still keep active are list ed below: ? clock generator ? 32.768 khz internal low speed rc oscillator (lirc ) clock ? 32.768 khz external low speed crystal oscillator ( l xt ) clock in power - down m o de , if the w o ke - up even occurred , the disabled clocks will be regenerat ed after pdwkpsc ( clk_pwrctl [23:8]) x 256 hxt cycle . c 1 c 2 r c r y s t a l c h i p b o a r d e x t e r n a l c r y s t a l c l o c k _ o u t x t _ i n / x 3 2 _ i n x t _ o u t / x 3 2 _ o u t
n uc505 june 3 0 , 2016 page 88 of 130 rev 1.0 6 nuc505 series datasheet general purpose i/o (gpio) 6.4 6.4.1 overview the nuc505 series has up to 52 general purpose i/o pins to be shared with other function pins depending on the chip configuration. the 52 pins are arranged in 4 ports named as pa, pb, pc, and pd. pa and pb ha ve 16 pins on port , p c has 15 pins on port , and p d has 5 pins on port. each of the 52 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each i/o pins can be configur ed by software individually as i nput or push - pull output mode. after the chip is reset, the i/o mode of all pins is input mode with no pull - up and pull - down enable (except pb.2, it is pull - up enable) . each i/o pin has a n individual pull - up and pull - down resistor which is about 40 k ? ~ 50 k ? for v dd and vss . user can set px_puen to control i/o pins to pull - up or pull - down. figure 6.4 - 1 i/o pin block diagram 6.4.2 features ? two i/o modes: ? push - pull output mode ? input only with high impendence mode ? cmos /schmitt trigger input selectable (refers sys_gpaibe register on trm ) ? i/o pin can be configured as interrupt source with edge setting p a d p i n [ n ] ( p x _ p i n ) p u l l s e l [ 0 ] ( p x _ p u e n ) p u l l s e l [ 1 ] ( p x _ p u e n ) m o d e [ n ] ( p x _ m o d e ) d o u t [ n ] ( p x _ d o u t ) n o t e : p x _ m e a n s p a _ , p b _ , p c _ , o r p d _
n uc505 june 3 0 , 2016 page 89 of 130 rev 1.0 6 nuc505 series datasheet ? i/o pin has individual internal pull - up resistor and pull - down resistor ? enabling the pin interrupt function will also enable the wake - up function
n uc505 june 3 0 , 2016 page 90 of 130 rev 1.0 6 nuc505 series datasheet timer c ontroller (t i m e r) 6.5 6.5.1 overview the timer controller includes four 32 - bit timers, timer0 ~ timer3, allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.5.2 features ? four sets of 32 - bit timers with 24 - bit up counter and on e 8 - bit prescale counter ? independent clock source for each timer ? provides o ne - shot, p eriodic , t oggle and c ontinuous c ounting operation modes ? time - out period = (period of timer clock input) * (8 - bit prescale counter+1) * cmpdat (timerx_cmp[23:0]) ? maximum co unting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24 - bit up counter value is readable through timer x _cnt (timer data register) ? support s event counting function to count the event from external pin ( tm0_cnt_out ~ tm3_cnt_out ) ? supports external capture pin (tm 0 _ext ~ tm 3 _ext) f or interval measurement ? supports external capture pin (tm 0 _ext ~ tm 3 _ext) to reset 24 - bit up counter ? supports chip wake - up from idle mode , power - d own mode and deep power - d own mode , if a timer interrupt signal is generated .
n uc505 june 3 0 , 2016 page 91 of 130 rev 1.0 6 nuc505 series datasheet pwm generator and capture timer (pwm) 6.6 6.6.1 overview the nuc505 series has one pwm generator that can support four channels pwm output or four channels input capture sharing the same pins (pwm_ch0/ pwm_ch1/pwm_ch2/pwm_ch3). the pwm generator has a 16 - bit pwm counter and comparator, and the pwm generator supports two standard pwm output modes: independent output mode and complementary output mode with 8 - bit d ead - time generator. each mode can be used as a timer and issues interrupt independently. in addition, it also has an 8 - bit prescaler and clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16) to support wide range clock frequency of pwm counter. for pwm output control unit, it supports polarity output function. the pwm generator also supports input capture function. it supports latch pwm counter value to corresponding register when input channel has a rising transition, falling transition or both transition is happened . after the capture feature is enabled , the capture always latche s pwm - counter to r capdat n when input channel has a rising transition and latched pwm - counter to fcapdat n when input channel has a falling transition. capture channel 0 interrupt is programmable by setting crlien0 (pwm_capctl01[1]) (rising latch interrupt en able) and cflien0 (pwm_capctl01[2]) (falling latch interrupt enable) to determine the condition o f interrupt occur. capture channel 1 has the same feature by setting crlien1 ( pwm_capctl01[17] ) and cflien1 ( pwm_capctl01[18] ) . the capture channel 2 & 3 has the same feature by setting crlien2 ( pwm_capctl23[1] ) , cflien2 ( pwm_capctl23[2] ) and crlien3 ( pwm_capctl23[17] ) , cflien3 ( pwm_capctl23[18] ) respectively. whenever capture issues interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this moment . there are only four interrupts from pwm. pwm 0 and capture 0 share the same interrupt; pwm 1 and ca pture 1 share the same interrupt and so on. therefore, pwm function and capture function in the same channel cannot be used at the same time. 6.6.2 features pwm function features 6.6.2.1 ? supports 4 pwm output channels with 16 - bit resolution ? supports 8 - bit prescaler and clock divider ? supports 4 pwm interrupts ? supports one - shot or auto - reload pwm counter operation mode ? supports 8 - bit dead - time capture function features 6.6.2.2 ? supports 4 capture input channels with 16 - bit resolution ? supports rising or falling capture condition ? supports 4 capture interrupts
n uc505 june 3 0 , 2016 page 92 of 130 rev 1.0 6 nuc505 series datasheet watchdog timer (wdt) 6.7 6.7.1 overview the watchdog timer is used to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, th e watchdog timer supports the function to wake up system from power - down mode . 6.7.2 features ? 18 - bit free running up counter for watchdog t imer time - out interval . ? selectable time - out interval (2 4 ~ 2 18 ) wdt_clk cycle and the time - out interval period is 32.5 ms ~ 8.224 s if wdt_clk = 32 khz. ? system kept in reset state for a period of (1 / wdt_clk) * 63 ? supports selectable watchdog t imer reset delay period, includ ing 1026 130 18 or 3 wdt_clk reset delay period. ? supports watchdog t imer time - out wake - up function when watchdog timer clock source is selected as 32 khz low - speed oscillator. window watchdog timer (wwdt) 6.8 6.8.1 overview the window watchdog timer is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.8.2 features ? 6 - bit down counter cntdat ( wwdt_cnt [5:0]) and 6 - bit compare value cmpdat ( wwdt_ctl [21:16]) to make the window period flexible ? selectable maximum 11 - bit wwdt clock prescale pscsel ( wwdt_ctl [11:8]) to make wwdt time - out interval variable
n uc505 june 3 0 , 2016 page 93 of 130 rev 1.0 6 nuc505 series datasheet real time clock (rtc) 6.9 6.9.1 overview the real time clock (rtc) block can be operated by independent power supply while the system power is off. the rtc uses a 32.768 khz external crystal (lxt) or internal oscillator (lirc) , and offers programmable time tick and alarm match interrupts. the data format of time and calendar messages are expressed in bcd format. a digital frequency compensation feature is available to compensate the frequency accuracy of external crystal oscillator (lxt) or internal oscillator (lirc) . the rtc controller also offers 32 bytes spare re gisters to sto re users important information . the wake - up sig nal is used to wake the system from idle mode , power - down mode and deep power - down mode. 6.9.2 features ? supports real time counter in rtc_time (hour, minute, second) and calendar counter in rtc_cal (year, month, day) for rtc time and calendar check ? supports alarm time (hour, minute, second) and calendar (year, month, day) settings in rtc_talm and rtc_calm ? selectable 12 - hour or 24 - hour time scale in rtc_clkfmt register ? supports leap year indication in rtc_leapyear register ? supports day of the week counter in rtc_weekday register ? frequency of rtc clock source compensate by rtc_freqadj register ? all time and calendar message expressed in bcd format ? supports periodic rtc time tick interrupt with 8 period i nterval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? supports rtc time tick and alarm match interrupt ? supports chip wake - up from idle mode , power - down mode and deep power - down mode while a rtc interrupt signal is generated ? supports 32 bytes spare registers and these registers values are preserved when rtc power domain is existed
n uc505 june 3 0 , 2016 page 94 of 130 rev 1.0 6 nuc505 series datasheet uart interface controller (uart) 6.10 6.10.1 overview the nuc505 series provide s three channels of universal asynchronous receiver/transmitters (uart). the uart controller performs a serial - to - parallel conversion on data received from the peripheral and a parallel - to - serial conversion on data transmitted from the cpu. each uart controller c hannel supports ten types of interrupts. the uart controller also supports irda si r, rs - 485 , auto - flow control function and auto - baud rate measuring f unction. 6.10.2 features ? full - duplex asynchronous communications ? separate s receive and transmit 16/16 (uart0) / 64 /64(uart1 and uart2) bytes entry fifo for data payloads ? support s hardware auto - flow control ( n cts and n rts) with uart1 and uart2 ? programmable receiver buffer trigger level ? support s programmable baud rate generator for each channel individually ? support s n cts and data wake - up function ? support s 8 - bit receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting dly ( uart_tout [ 15:8 ] ) ? supports auto - baud rate measurement ? support s break error, frame error, parity error and receiv e/ transmit buffer overflow detect ion function ? fully programmable serial - interface features ? programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation ? support s irda sir function mode ? supports for 3/16 bit duration for normal mode ? support s lin function mode ( only uart 1 /uart 2 with lin function) ? supports lin m aster / s lave mode ? supports programmable break generation function for transmitter ? supports break detect ion function for receiver ? support s rs - 485 function mode ? supports rs - 485 9 - bit mode ? supports hardware or software enable s to program n rts pin to control rs - 485 transmission direction
n uc505 june 3 0 , 2016 page 95 of 130 rev 1.0 6 nuc505 series datasheet i 2 c serial interface controller (master/slave) 6.11 6.11.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a slave synchronously to scl on the sda line on a byte - by - byte basis. eac h data byte is 8 - bit long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to the following figure for more detail s about i 2 c b us timing. figure 6.11 - 1 i 2 c bus timing the device on - chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. to enable this port, the bit i2cen ( i2c _ctl[6]) should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda and scl. pull up resistor is needed for i 2 c operation as these are open drain pins. wh en the i/o pins are used as i 2 c port, user must set the pins function to i 2 c in advance. s t o p s d a s c l s t a r t r e p e a t e d s t a r t s t o p
n uc505 june 3 0 , 2016 page 96 of 130 rev 1.0 6 nuc505 series datasheet 6.11.2 features the nuc505 series provide s two channels of i 2 c. the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the m ain features of the bus include : ? master/slave mode and general call mode ? bidirectional data transfer between masters and slaves ? multi - master bus ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to stretch and un - stretch serial transfer ? built - in a 14 - bit time - out counter will request the i 2 c interrupt if the i 2 c bus hangs up and time - out counter overflows. ? programmable divider allow ing for versatile rate control ? supports 7 - bit addressing mode ? s upport s multiple address recognition ( f our slave address es with mask option) ? supports address match wake - up function
n uc505 june 3 0 , 2016 page 97 of 130 rev 1.0 6 nuc505 series datasheet serial peripheral interface (spi ) 6.12 6.12.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol that operates in full duplex mode. devices communicate in master/slave mode with the 4 - wire bi - dir ection interface. the nuc505 series contains one set of spi controller performing a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. a lso, the spi controller can be configured as a master or a slave device. 6.12.2 features ? support s m aster or slave mode operation ? configurable bit length of a transfer word from 8 to 32 - bit ? provide s separate 8 - level depth transmit and receive fifo buffers ? support s msb first or lsb first transfer sequence ? support s byte reorder function ? support s b yte or w ord s uspend mode ? support s 3 - wire, no slave select signal, bi - direction interface ? up to 2 sets of spi controllers
n uc505 june 3 0 , 2016 page 98 of 130 rev 1.0 6 nuc505 series datasheet spi memory interface controller ( spim) 6.13 6.13.1 overview the spi memory interface c ontroller performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data received from cpu. this controller can drive up to 2 external peripherals ( e mbedded spi flash or e xternal spi flash) and act as a spi master. it can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag. the active level of device/slave select signal can be chosen to low active or high active, which depends on the peripheral. writing a divisor into the spim_ctl1 register can program the frequency of serial clock output to the peripheral. this controller contains four 32 - bit transmit/receive buffers, and can provide 1 to 4 burst mode operation. the number of bits in each transaction can be 8, 16, 24, or 32 ; data can be transmit ted /receive d up to four successive transactions in one transfer. 6.13.2 features ? support s spi master mode ? support s dma mode ( dma write and dma read), direct memory map (dmm) m ode, an d i / o m ode ? 8 - , 16 - , 24 - , and 32 - bit length of transaction ? supports standard (1 - bit), dual (2 - bit), and quad (4 - bit) i/o transfer mode ? provide s burst mode operation , which can transmit/receive data up to four successive transactions in one transfer ? two slave /device select lines ( e mbedded spi flash or e xternal spi flash) ? fully static synchronous design with one clock domain
n uc505 june 3 0 , 2016 page 99 of 130 rev 1.0 6 nuc505 series datasheet i 2 s controller with i nternal a udio codec (i 2 s) 6.14 6.14.1 overview the i 2 s controller consists of i 2 s protocol interface to internal audio codec and support s to use external audio codec. the i 2 s controller includes t wo 16 word s fifo for transfer path and receiver path respectively and is capable of handling 8 , 16, 24, or 32 bit s word sizes sample . the structure of internal audio codec is a delta - sigma 24 - bit codec with microphone input, audio line - in input, and headphone output. 6.14.2 features i 2 s controller ? supports m aster mode and s lave mode ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes sample ? supports mono and s tereo audio data ? supports i 2 s and most significant bit ( msb ) justified data format ? supports pcm - a and pcm - b data format ? provides t wo 16 word s fifo, one for transmit ting and the other for receiv ing ? generates interrupt requests when fifo levels cross a programmable boundary ? supports tx dma function for transmitting and rx dma function r eceiv ing ? supports rx data power measurement ? supports connecting to external audio codec internal codec ? supports mono microphone input and stereo audio line - in input ? supports stereo headphone output ? supports stereo and mono mode ? features of adc total - harmonic - distortion with noise (thd+n): - 80 db dynamic - range (dr) and signal - to - noise ratio (snr): 90 db (a - weighted) ? features of dac (headphone out with 32? loading) total - harmonic - distortion with noise (thd+n): - 60 db dynamic - range (dr) and signal - to - noise ratio (snr): 93 db (a - weighted) ? supports sampling rate with 8 khz, 11.025 khz, 12 khz, 16 khz, 22.05 khz, 24 khz, 32 khz, 44.1 khz, 48 khz, and 96 khz
n uc505 june 3 0 , 2016 page 100 of 130 rev 1.0 6 nuc505 series datasheet usb 2.0 device controller (usbd) 6.15 6.15.1 overview the usb device controller interfaces the ahb bus and the utmi bus. the usb controller contains both the ahb master interface and ahb slave interface. cpu programs the usb controller registers through the ahb slave interface. for in or out transfer , the usb device controller needs to write data to memory or read data from memory through the ahb master interface. the usb device controller is complaint with usb 2.0 specification and it contains 12 configurable endpoints in addition to control endpoint . these e ndpoints could be configured to bulk, interrupt or iso. the usb device controller has a built - in dma to relieve the load of cpu. 6.15.2 features ? usb specification reversion 2.0 compliant ? supports 12 configurable endpoints in addition to control endpoin t ? each of the endpoints can be isochronous, bulk or interrupt and either in or out direction ? three different operation modes of an in - endpoint auto validation mode, manual validation mode, fly mode ? supports dma operation ? 2048 bytes configurable ram used as endpoint buffer ? supports endpoint maximum packet size up to 1024 bytes
n uc505 june 3 0 , 2016 page 101 of 130 rev 1.0 6 nuc505 series datasheet usb 1.1 host controller ( usbh ) 6.16 6.16.1 overview the nuc505 series is equipped with one usb 1.1 host controller (usbh) that supports open host controller interface (openhci, ohci) specification and register - level description of a host controller to manage the devices and data transfer of universal serial bus (usb). the usbh supports an integrated root hub with a usb port, a dma for real - time data transfer b etween system memory and usb bus, port power control and port overcurrent detection. the usbh is responsible for detecting the connect and disconnect of usb devices, managing data transfer, collecting status and activity of usb bus, providing power control and detecting overcurrent of attached usb devices. 6.16.2 features ? supports universal serial bus (usb) specification revision 1.1. ? supports open host controller interface (openhci) specification revision 1.0. ? supports both full - speed (12mbps) and low - speed (1.5 mbps) usb devices. ? supports control, bulk, interrupt and isochronous transfers. ? supports an integrated root hub. ? s upports one usb host port in lqfp48 or lqfp64 and two usb host ports in qfn88 ? supports port power control and port overcurrent detection. ? supports dma for real - time data transfer.
n uc505 june 3 0 , 2016 page 102 of 130 rev 1.0 6 nuc505 series datasheet secure - digital host controller (sdhc) 6.17 6.17.1 overview the secure - digital host controller (sdh controller) includes a dmac (direct memory access controller ) unit and a sd unit. the dmac unit provides a dma (direct memory access) function for sd to exchange data between system memory and shared buffer (128 bytes), and the sd unit controls the interface of sd/sdhc /mmc . the sd host controller can support sd/sdhc /mmc with dmac to provide a fast data transfer between system me mory and cards. 6.17.2 features ? supports single dma channel. ? supports hardware scatter - gather function. ? using single 128 bytes shared buffer for data exchange between system memory and cards. ? interface with dmac for register read/write and data transfer. ? support s sd/sdhc /mmc card. ? the frequency of hclk should be higher than the frequency of peripheral clock.
n uc505 june 3 0 , 2016 page 103 of 130 rev 1.0 6 nuc505 series datasheet 12 - bit a nalog - to - digital converter (a dc ) 6.18 6.18.1 overview the nuc505 series contains one 12 - bit successive approximation analog - to - digital converter ( adc) with 8 single - end external input channels (adc_ch0, adc_ch1, adc_ch7) . the adc_ch0 has an internal 10 k ? resistor divider for battery detection. the adc_ch2 also supports key pad comparator function. user can control the a/d conversion by setting the swtrg ( adc _ctl[0]) . 6.18.2 feature s ? analog input voltage range: 0~ av dd adc . ? 12 - bit resolution and 10 - bit accuracy guaranteed. ? up to 8 single - end analog input channels. ? adc clock frequency up to 16 mhz. ? up to 1 m sps conversion rate when using in adc_ch1 channel. ? up to 200 k sps conversion rate when using in adc_ch2, adc_ch7 channels. ? configurable adc internal sampling time. ? supports key pad compar ator (adc_ch2). ? built - in 10 k? resistor divider for battery detection (adc_ch0).
n uc505 june 3 0 , 2016 page 104 of 130 rev 1.0 6 nuc505 series datasheet 7 electrical character istics absolute maximum ratings 7.1 symbol parameter min max unit v dd ? v ss dc power supply - 0.3 + 4 .0 v v in input voltage v ss - 0.3 v dd + 0.3 v 1/t clcl oscillator frequency 12 mhz t a operating temperature - 40 + 85 t st storage temperature - 55 +150 i dd maximum current into v dd - 1 6 0 ma i ss maximum current out of v ss 1 6 0 ma i io maximum current sunk by a i/o pin i/o pin[*2, 3, 4] ma maximum current sourced by a i/o pin i/o pin[*2, 3, 4] ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: 1. exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device. 2. 4ma: pa.14, pa.15, pb.0, pb.1, pb.2, pb.3, pb.4, pb.5, pb.6, pb.7, pb.8, pb.9, pb.10, pb.11, pc.8, pc.9, pc.10, pc.11, pc.12, pd.0, pd.1 3. 8ma: pa.8, pa.9, pa.10, pa.11, pa.12, pa.13, pb.12, pb.13, pb.14, pb.15, pc.0, pc.1, pc.2, pc.3, pc.4, pc.5, pc.6, pc.7, pc.13, pc.14 4. can setting strength for 2ma, 6.5ma, 8.7ma, 13ma, 15.2ma, 19.5ma, 21.7m a, 26.1ma: pa.0, pa.1, pa.2, pa.3, pa.4, pa.5, pa.6, pa.7, pd.2, pd.3, pd.4
n uc505 june 3 0 , 2016 page 105 of 130 rev 1.0 6 nuc505 series datasheet dc characteristics 7.2 ( v dd - v ss = 3 ~ 3.6 v, t a = 25 ? c) s ymbol parameter specification test conditions min. typ. max. unit v dd operation v oltage 3 3.3 3.6 v v ss av ss power ground - 0.3 - - v v dd 12 core logic and i/o buffer pre - driver voltage 1.08 1.2 1.32 v v bat rtc power supply 2 - 3.6 v i bat_ex external crystal rtc supply current - 4 - ua i bat_in i nternal rc rtc supply current 0.1 0.6 0.9 ua f int_rc internal rc frequency 15 32 90 khz v oh high level output voltage 2.4 - - v v ol low level output voltage - - 0.4 v v ih input high voltage 2.0 - - v v il input low voltage - - 0.8 v v th switch threshold 0.87 1.05 1.2 v schmitt - falling - trigger 1.65 1.9 2.1 v schmitt - rising - trigger r pu input pull - up resist 32 53 120 k in = v ss
n uc505 june 3 0 , 2016 page 106 of 130 rev 1.0 6 nuc505 series datasheet s ymbol parameter specification test conditions min. typ. max. unit r pd input pull - down resistance 37 49 120 k v in = v dd i l input leakage current - 10 - 10 ua i oz tri - state output leakage current - 10 - 10 ua i ol1 low level sink current [*1] 4 - - ma v ol = 0.4v i ol2 8 - - ma i ol3 2 6.5 8.7 13 15.2 19.5 21.7 26.1 - - ma i oh1 high level source current [* 2 ] 4 - - ma v oh = 2 .4v i oh2 8 - - ma i oh3 2 6.5 8.7 13 15.2 19.5 21.7 26.1 - - ma i dd1 v dd = 3.3v , operating current normal run mode while(1){} executed from spi flash or ram - 18.83 - ma hxt 12mhz lxt pll 96mhz all digital module code ? ? ? ? spi i d d2 - 27.33 - ? ? ? ? spi i dd3 - 25.38 - ? ? ? ? ram i dd4 - 32.13 - ? ? ? ? ram i dd5 - 4.53 ? ? ? ? spi i dd6 - 6.47 ? ? ? ? spi i dd7 5.23 ? ? ? ? ram i dd8 5.94 ? ? ? ? ram
n uc505 june 3 0 , 2016 page 107 of 130 rev 1.0 6 nuc505 series datasheet s ymbol parameter specification test conditions min. typ. max. unit i idle1 v dd = 3.3v , operating current idle mode at 12 m hz - 17 - ma hxt rtc pll all digital module ? ? ? ? i idle2 - 12.3 - ? ? ? ? i pwd v dd =3.3v , standby current power - down (deep sleep) mode 700 - - ua hxt rtc pll ram retention ? ? ? ? note: 1. 4ma: pa.14, pa.15, pb.0, pb.1, pb.2, pb.3, pb.4, pb.5, pb.6, pb.7, pb.8, pb.9, pb.10, pb.11, pc.8, pc.9, pc.10, pc.11, pc.12, pd.0, pd.1 2. 8ma: pa.8, pa.9, pa.10, pa.11, pa.12, pa.13, pb.12, pb.13, pb.14, pb.15, pc.0, pc.1, pc.2, pc.3, pc.4, pc.5, pc.6, pc.7, pc.13, pc.14 3. can setting strength for 2ma, 6.5ma, 8.7ma, 13ma, 15.2ma, 19.5ma, 21.7ma, 26.1ma: pa.0, pa.1, pa.2, pa.3 , pa.4, pa.5, pa.6, pa.7, pd.2, pd.3, pd.4
n uc505 june 3 0 , 2016 page 108 of 130 rev 1.0 6 nuc505 series datasheet ac electrical characteristics 7.3 7.3.1 external 12 mhz crystal note: duty cycle is 50%. parameter symbol min. typ. max. units conditio n clock high time t chcx - 41.6 - ns clock low time t clcx - 41.6 - ns clock rise time t clch - - 25 ns clock fall time t chcl - - 25 ns 7.3.2 external 12 mhz high speed oscillator symbol parameter condition min. typ. max. unit f hxt input clock frequency external crystal for x in 12 mhz t a temperature - - 40 - 85 v hxt v dd - 3.3 v i hxt operating current 12 mhz@ v dd = 3.3 v - 3 - ma 7.3.3 typical crystal application circuits crystal oscillator c apacitance v alues r esistance v alues 12 mhz 20pf 1 m ? 32.768 khz 33pf 10 m ? t c l c l t c l c x t c h c x t c l c h t c h c l
n uc505 june 3 0 , 2016 page 109 of 130 rev 1.0 6 nuc505 series datasheet figure 7.3 - 1 typical crystal application circuit 7.3.4 internal 32 khz low speed oscillator parameter condition min. typ. max. unit supply voltage - 3 - 3.6 v center frequency - - 32 - k hz operating current v dd = 3.3 v - 0.5 - ua 1 2 m h z c r y s t a l 2 0 p 2 0 p x t 1 _ o u t x t 1 _ i n 1 0 m 1 m 3 2 . 7 6 8 k h z c r y s t a l 3 3 p 3 3 p x t 3 2 _ o u t x t 3 2 _ i n
n uc505 june 3 0 , 2016 page 110 of 130 rev 1.0 6 nuc505 series datasheet analog characteristics 7.4 7.4.1 specifications of 12 - bit saradc symbol parameter specifications test conditions min typ max unit a vdd _ adc operating voltage 2.7 3.3 3.6 v r adc resolution - - 12 bit v ref reference voltage 2 - a vdd _ adc v v in adc input voltage 0 - v ref v r in a nalog input impedance 2 m ? f sps sampling rate - - 1m hz adc clock = 16mhz free running conversion (adc_ch1) - - 200k hz adc clock = 3.2 mhz free running conversion (adc_ch2, adc_ch3, adc_ch4, adc_ch5, adc_ch6, adc_ch7) e q gain error (transfer gain ) - - 2 - 4 lsb e a absolute error - 3 - lsb inl integral non - linearity error - 3 - lsb dnl differential non - linearity error - 1 - +1.5 lsb e o offset error 1 3 lsb snr s/n - 62 - db - total harmonic distortion - 62 - db note: 1. the performance measurement is in adc only condition (all other module are in reset statue). 2. design by guarantee, no test in production.
n uc505 june 3 0 , 2016 page 111 of 130 rev 1.0 6 nuc505 series datasheet note: the inl is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. a calibrated transfer curve means it has calibrate d the offset and gain error from the actual transfer curve. 1 2 3 4 5 6 4 0 9 5 4 0 9 4 7 4 0 9 3 4 0 9 2 i d e a l t r a n s f e r c u r v e a c t u a l t r a n s f e r c u r v e o f f s e t e r r o r e o a n a l o g i n p u t v o l t a g e ( l s b ) 4 0 9 5 a d c o u t p u t c o d e o f f s e t e r r o r e o g a i n e r r o r e g e f ( f u l l s c a l e e r r o r ) = e o + e g d n l 1 l s b
n uc505 june 3 0 , 2016 page 112 of 130 rev 1.0 6 nuc505 series datasheet 7.4.2 specifications of 24 - bit delta - sigma codec symbol parameter specifications test conditions min. typ max. unit reference vmid - 0.5*a vdd _ co dec - v microphone bias bias voltage - 0.75*a vdd _ c odec - v maximum output current - - 3 ma capacitive load - - 50 pf line input resolution - 24 - bit thd total harmonic distortion - - 80 - 70 db dr dynamic range 80 90 - db - 60db input, a - weighted snr s/n 80 90 - db channel separation - 100 - db channel matching - 0.2 - db vfs full scale output voltage - 0.93* a vdd _ codec / 3.3 - db input impedance 10 - - k input capacitor - 10 - pf headphone output thd total harmonic distortion - - 80 - db rl = 0 , po = 10mw thd total harmonic distortion - - 60 - db rl = 32 , po = 10mw snr s/n 90 93 - db a - weighted power supply current (no pll, no loading) a vdd _ codec - 8 - ma
n uc505 june 3 0 , 2016 page 113 of 130 rev 1.0 6 nuc505 series datasheet symbol parameter specifications test conditions min. typ max. unit a vdd _ hp - 4 - ma note: the performance measurement is in codec only condition (all other module are in reset statue). 7.4.3 specification of ldo symbol parameter min. typ max. unit note v dd input voltage 1.62 3.3 3.6 v a vdd _ ldo input voltage v ldo output voltage - 10% 1.2 +10% v t a temperature - 4 0 25 85 e cap external capacitor - 4.7 - f notes: 1. it is recommended a 0.1f bypass capacitor is connected between v dd and the closest v ss pin of the device. 2. for ensuring power stability, a 4.7 f or higher capacitor must be connected between ldo_cap pin and the closest v ss pin of the device.
n uc505 june 3 0 , 2016 page 114 of 130 rev 1.0 6 nuc505 series datasheet 7.4.4 specification of low voltage reset symbol parameter min. typ max. unit test condition v dd supply voltage 0 - 3.6 v t a temperature - 40 25 85 i lvr quiescent current - 25 4 0 ua v dd =3.3v v lvr threshold voltage 2. 16 2. 4 2. 64 v t a = - 45 ~ 85 7.4.5 specifications of power - on reset symbol parameter min. typ max. unit test condition t a temperature - 40 25 85 i por quiescent current - 33 50 ua v dd >reset voltage v por reset voltage 1.6 2 2.4 v t a = - 40 ~ 85 v por v dd start voltage to ensure power - on reset - - 100 m v rpv dd v dd raising rate to ensure power - on reset 0.025 - - v /ms t por minimum time for vdd stays at vpor to ensure power - on reset 0.5 - - ms
n uc505 june 3 0 , 2016 page 115 of 130 rev 1.0 6 nuc505 series datasheet figure 7.4 - 1 power - up ramp condition t p o r r r v d d v p o r v d d t i m e
n uc505 june 3 0 , 2016 page 116 of 130 rev 1.0 6 nuc505 series datasheet 7.4.6 usb phy specifications usb dc electrical characteristics 7.4.6.1 symbol parameter conditions min. typ max. unit v ih input high (driven) 2.0 - - v v il input low - - 0.8 v v di differential input sensitivity usb_ dp - usb_dm 0.2 - - v v cm differential common - mode range includes v di range 0.8 - 2.5 v v se single - ended receiver threshold 0.8 - 2.0 v receiver hysteresis - 400 - mv v ol output low (driven) 0 - 0.3 v v oh output high (driven) 2.8 - 3.6 v v crs output signal cross voltage 1.3 - 2.0 v r pu pull - up resistor 1.425 - 1.575 k v trm pull - down resistor 14.25 - 15.75 k z drv termination voltage for upstream port pull up (rpu) 3.0 - 3.6 v c in driver output resistance steady state drive* 28 - 49.5 v ih transceiver capacitance pin to v ss - - 20 pf note: driver output resistance does not include series resistor resistance.
n uc505 june 3 0 , 2016 page 117 of 130 rev 1.0 6 nuc505 series datasheet usb full - speed driver electrical characteristics 7.4.6.2 symbol parameter conditions min. typ max. unit t fr rising time cl = 50p 4 - 20 ns t ff falling time cl = 50p 4 - 20 ns t frff rising and falling time matching t frff = t fr / t ff 90 - 111.11 % usb high - speed driver electrical characteristics 7.4.6.3 symbol parameter conditions min. typ max. unit t fr rising time cl = 5p 500 ns t ff falling time cl = 5p 500 ns t frff rising and falling time matching t frff = t fr / t ff 90 111 %
n uc505 june 3 0 , 2016 page 118 of 130 rev 1.0 6 nuc505 series datasheet 7.4.7 i 2 c dynamic characteristics symbol parameter standard mode[1][2] fast mode[1][2] unit min. max. min. max. t low scl low period 4.7 - 1.2 - us t high scl high period 4 - 0.6 - us t su; sta repeated start condition setup time 4.7 - 1.2 - us t hd; sta start condition hold time 4 - 0.6 - us t su; sto stop condition setup time 4 - 0.6 - us t buf bus free time 4.7[3] - 1.2[3] - us t su;dat data setup time 250 - 100 - ns t hd;dat data hold time 0[4] 3.45[5] 0[4] 0.8[5] us t r scl/sda rise time - 1000 20+0.1cb 300 ns t f scl/sda fall time - 300 - 300 ns c b capacitive load for each bus line - 400 - 400 pf notes: 1. guaranteed by design, not tested in production. 2. hclk must be higher than 2 mhz to achieve the maximum standard mode i 2 c frequency. it must be higher than 8 mhz to achieve the maximum fast mode i 2 c frequency. 3. i 2 c controller must be retriggered immediately at slave mode after receiving stop condition. 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 5. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. figure 7.4 - 2 i 2 c timing diagram t b u f s t o p s d a s c l s t a r t t h d ; s t a t l o w t h d ; d a t t h i g h t f t s u ; d a t r e p e a t e d s t a r t t s u ; s t a t s u ; s t o s t o p t r
n uc505 june 3 0 , 2016 page 119 of 130 rev 1.0 6 nuc505 series datasheet 7.4.8 spi dynamic characteristics symbol parameter min. typ. max. unit spi master mode (v dd = 3.0 v ~ 3.6 v, 0 pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 4.5 - - ns t v data output valid time - 2 4 ns spi slave mode (v dd = 3.0 v ~ 3.6 v, 0 pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 4.5 - - ns t v data output valid time - 18 24 ns figure 7.4 - 3 spi master mode timing diagram c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
n uc505 june 3 0 , 2016 page 120 of 130 rev 1.0 6 nuc505 series datasheet figure 7.4 - 4 spi slave mode timing diagram c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
n uc505 june 3 0 , 2016 page 121 of 130 rev 1.0 6 nuc505 series datasheet 7.4.9 i 2 s dynamic characteristics symbol parameter min. max. unit test conditions t h(ws) i2s clock high time 42 - ns master fpclk = 12.288 mhz, data: 24 bits, audio frequency = 48 khz t su(ws) i2s clock low time 37 - t h(ws) lrclk valid time 7 - master mode ducy (sck) lrclk hold time 1 - master mode t su(sd_mr) lrclk setup time 34 - slave mode t su(sd_sr) lrclk hold time 0 - slave mode t h(sd_mr) i2s slave input clock duty cycle 25 75 % slave mode t h(sd_sr) data input setup time 0 - ns master receiver t v(sd_st) 0 - slave receiver t h(sd_st) data input hold time 0 - master receiver t v(sd_mt) 0 - slave receiver t h(sd_mt) data output valid time - 32 slave transmitter (after enable edge) t h(ws) data output hold time 16 - slave transmitter (after enable edge) t su(ws) data output valid time - 5 master transmitter (after enable edge) t h(ws) data output hold time 0 - master transmitter (after enable edge)
n uc505 june 3 0 , 2016 page 122 of 130 rev 1.0 6 nuc505 series datasheet figure 7.4 - 5 i2s master mode timing diagram figure 7.4 - 6 i 2 s slave mode timing diagram t w ( c k h ) t w ( c k l ) t h ( l r c l k ) t v ( l r c l k ) t h ( s d _ s t ) l s b t r a n s m i t ( 2 ) m s b t r a n s m i t b i t n t r a n s m i t l s b t r a n s m i t l s b r e c e i v e ( 2 ) m s b r e c e i v e b i t n r e c e i v e l s b r e c e i v e t s u ( s d _ m r ) t h ( s d _ m r ) s d t r a n s m i t s d r e c e i v e l r c l k o u t p u t t v ( s d _ s t ) b c l k o u t p u t t w ( c k h ) t w ( c k l ) t h ( l r c l k ) t s u ( l r c l k ) t h ( s d _ s t ) l s b t r a n s m i t ( 2 ) m s b t r a n s m i t b i t n t r a n s m i t l s b t r a n s m i t l s b r e c e i v e ( 2 ) m s b r e c e i v e b i t n r e c e i v e l s b r e c e i v e t s u ( s d _ s r ) t h ( s d _ s r ) s d t r a n s m i t s d r e c e i v e l r c l k i n p u t t v ( s d _ s t ) b c l k i n p u t
n uc505 june 3 0 , 2016 page 123 of 130 rev 1.0 6 nuc505 series datasheet 8 application circuit a v s s a d c a v d d c o d e a v c c d v c c v s s 0 . 1 u f f b f b p o w e r c r y s t a l n u c 5 0 5 s e r i e s c d e v i c e l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t 0 . 1 u f u a r t r x d t x d s p e a k e r r h p _ o u t l h p _ o u t 5 v c c u s b h o s t d v c c 1 0 u f / 1 0 v 1 0 k n r e s e t 1 2 m h z c r y s t a l 2 0 p 2 0 p x t 1 _ o u t x t 1 _ i n v d d v s s i 2 c l k d a t a i 2 c 1 _ s d a i 2 c 1 _ s c l 4 . 7 k d v c c 4 . 7 k d v c c a v d d u s b n r e s e t i c e _ c l k s w d i n t e r f a c e a v d d a d c 3 2 . 7 6 8 k h z c r y s t a l 3 3 p 3 3 p x 3 2 _ o u t x 3 2 _ i n l d o _ c a p 4 . 7 u f r e s e t c i r c u i t v d d v s s s p i d e v i c e c s c l k m i s o s p i 1 _ s s m o s i s p i 1 _ c l k s p i 1 _ m i s o s p i 1 _ m o s i d v c c u s b d e v i c e u s b _ v d d 3 3 _ c a p 1 u f u s b _ d - u s b _ d + u s b _ v b u s a v d d h p v b a t v d d l d o _ a v s s a v s s h p v d d 1 0 m 1 m a u d i o _ r _ i n a u d i o _ l _ i n l i n e i n c u r r e t p r o t e c t i c g p i o u s b h _ d - u s b h _ d + i c e _ c l k v s s
n uc505 june 3 0 , 2016 page 124 of 130 rev 1.0 6 nuc505 series datasheet 9 package dimensions lqfp 48 l (7x7x1.4mm footprint 2.0mm) 9.1
n uc505 june 3 0 , 2016 page 125 of 130 rev 1.0 6 nuc505 series datasheet qfn 4 8 ( 7 x 7 x 0. 8 mm) 9.2
n uc505 june 3 0 , 2016 page 126 of 130 rev 1.0 6 nuc505 series datasheet lqfp 64l ( 7 x 7 x1.4mm footprint 2.0mm) 9.3
n uc505 june 3 0 , 2016 page 127 of 130 rev 1.0 6 nuc505 series datasheet qfn 88 (10x10x 0.9 mm) 9.4
n uc505 june 3 0 , 2016 page 128 of 130 rev 1.0 6 nuc505 series datasheet
n uc505 june 3 0 , 2016 page 129 of 130 rev 1.0 6 nuc505 series datasheet 10 revision history date revision description 2014.04.23 1.0 1 preliminary version 2015.05.28 1.0 2 1. added new part number : nuc505dla , nuc505yla , and nuc505dsa in chapter 4. 2. updated embedded spi flash memory size to 512 kb for new part number . 2015.11.04 1.04 1. added a note to indicate that nuc505ds13y only support s headphone out in section 4.1.1 . 2. added a note to indicate the packages are not pin - to - pin compatible in section 4.1.1 . 3. added section 9.2 qfn 4 8 ( 7 x 7 x 0. 8 mm) package s pecification . 4. added part number nuc505yla2y in section 4.1.1 , 4.2.4 , and 4.3.4 . 5. replaced power mode name of sleep mode and deep - sleep mode with idle m ode and power - down mode respectively. 201 6 . 05 .0 9 1.0 5 1. added a note to pin diagram and pin description for qfn 48/88 - pin packages. 201 6 . 0 6 . 30 1.0 6 1. corrected t he typo in the pin configuration section 4.2.4 / 4.2.5 / 4.2.6 and pin description section 4.3.5 .
n uc505 june 3 0 , 2016 page 130 of 130 rev 1.0 6 nuc505 series datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usage inclu des, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, al l types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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